User`s manual

52
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37281MAH–XXXSP,M37281MFH–XXXSP
M37281MKH–XXXSP,M37281EKSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
Note: VREF indicates the reference voltage (= Vcc).
Fig. 8.8.3 Changes in A-D Conversion Register and Comparison Voltage during A-D Conversion
8.8.6 Conversion Method
➀ Set bit 7 of the interrupt input polarity register (address 021216) to
“1” to generate an interrupt request at completion of A-D conver-
sion.
➁ Set the A-D conversion · INT3 interrupt request bit to “0” (even
when A-D conversion is started, the A-D conversion · INT3 inter-
rupt reguest bit is not set to “0” automatically).
➂ When using A-D conversion interrupt, enable interrupts by setting
A-D conversion · INT3 interrupt request bit to “1” and setting the
interrupt disable flag to “0.”
➃ Set the VCC connection selection bit to “1” to connect VCC to the
resistor ladder.
➄ Select analog input pins by the analog input selection bit of the
A-D control register.
➅ Set the A-D conversion completion bit to “0.” This write operation
starts the A-D conversion. Do not read the A-D conversion register
during the A-D conversion.
➆ Verify the completion of the conversion by the state (“1”) of the
A-D conversion completion bit, the state (“1”) of A-D conversion ·
INT3 interrupt reguest bit, or the occurrence of an A-D conversion
interrupt.
➇ Read the A-D conversion register to obtain the conversion results.
Note : When the ladder resistor is disconnect from VCC, set the VCC connec-
tion selection bit to “0” between steps ➆ and ➇.
8.8.7 Internal Operation
When the A-D conversion starts, the following operations are auto-
matically performed.
➀ The A-D conversion register is set to “0016.”
➁ The most significant bit of the A-D conversion register becomes
“1, ” and the comparison voltage “Vref” is input to the comparator.
At this point, Vref is compared with the analog input voltage “VIN .”
➂ Bit 7 is determined by the comparison results as follows.
When Vref < VIN : bit 7 holds “1”
When Vref > VIN : bit 7 becomes “0”
With the above operations, the analog value is converted into a digi-
tal value. The A-D conversion terminates in a maximum of 50 ma-
chine cycles (12.5 µs at f(XIN) = 8 MHz) after it starts, and the con-
version result is stored in the A-D conversion register.
An A-D conversion interrupt request occurs at the same time as A-D
conversion completion, the A-D conversion · INT3 interrupt request
bit becomes “1.” The A-D conversion completion bit also becomes
“1.”
Table 8.8.1 Expression for Vref and VREF
A-D conversion register contents “n”
(decimal notation)
0
1 to 255
Vref (V)
0
VREF
2
V
REF
512
V
REF
2
V
REF
4
V
REF
512
V
REF
2
V
REF
4
V
REF
8
V
REF
512
V
REF
2
V
REF
4
V
REF
8
V
REF
512
V
REF
256
12
3
45678
1
0000000
12 100000
10000001
12345671
–
–
±
–
±±
00000 000
Contents of A-D conversion register Reference voltage (Vref) [V]
0
A-D conversion start
1st comparison start
3rd comparison start
8th comparison start
2nd comparison start
Digital value corresponding to
analog input voltage.
A-D conversion completion
(8th comparison completion)
±±±
–
±
.......
: Value determined by mth (m = 1 to 8) result
m
.....
VREF
256
✕ (n – 0.5)