User`s manual
33
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
M37281MAH–XXXSP,M37281MFH–XXXSP
M37281MKH–XXXSP,M37281EKSP
Function
In conformity with Philips I
2
C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I
2
C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at φ
= 4 MHz)
Table 8.6.1 Multi-master I
2
C-BUS Interface Functions
Item
Format
Communication mode
SCL clock frequency
φ
: System clock = f(XIN)/2
Note : We are not responsible for any third party’s infringement of patent rights
or other rights attributable to the use of the control function (bits 6 and 7
of the I
2
C control register at address 00F916) for connections between
the I
2
C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2).
8.6 MULTI-MASTER I
2
C-BUS INTERFACE
The multi-master I
2
C-BUS interface is a serial communications cir-
cuit, conforming to the Philips I
2
C-BUS data transfer format. This
interface, offering both arbitration lost detection and a synchronous
functions, is useful for the multi-master serial communications.
Figure 8.6.1 shows a block diagram of the multi-master I
2
C-BUS in-
terface and Table 8.6.1 shows multi-master I
2
C-BUS interface func-
tions.
This multi-master I
2
C-BUS interface consists of the I
2
C address reg-
ister, the I
2
C data shift register, the I
2
C clock control register, the I
2
C
control register, the I
2
C status register and other control circuits.
Fig. 8.6.1 Block Diagram of Multi-master I
2
C-BUS Interface
I
2
C address register (S0D)
b
7b
0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
N
o
i
s
e
e
l
i
m
i
n
a
t
i
o
n
c
i
r
c
u
i
t
S
e
r
i
a
l
d
a
t
a
(
S
D
A
)
Add
ress comparator
b7
I
C
d
ata s
hif
t reg
i
ster
b
0
D
a
t
a
c
o
n
t
r
o
l
c
i
r
c
u
i
t
I
2
C
c
l
o
c
k
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
2
)
S
y
s
t
e
m
c
l
o
c
k
(φ)
I
nterrupt
generating
circuit
I
nterrupt
request signal
(IICIRQ)
b7
M
S
T
TRX
B
B
PIN
A
L
AAS
AD
0
L
R
B
b0
I
C
s
t
a
t
u
s
r
e
g
i
s
t
e
r
(
S
1
)
b
7b
0
BSEL1 BSEL0
1
0
B
I
T
S
A
D
ALS
B
C
2B
C
1BC0
I
2
C
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
1
D
)
Bi
t counter
B
B
c
i
r
c
u
i
t
C
l
o
c
k
c
o
n
t
r
o
l
c
i
r
c
u
i
t
N
o
i
s
e
e
l
i
m
i
n
a
t
i
o
n
c
i
r
c
u
i
t
S
e
r
i
a
l
c
l
o
c
k
(
S
C
L
)
b
7b0
ACK
A
C
K
B
I
T
FAST
MODE
CCR4 CCR3 CCR2 CCR1 CCR0
I
nterna
l
d
ata
b
us
C
l
o
c
k
d
i
v
i
s
i
o
n
S
0
AL
circuit
E
S
O
2
2