User`s manual

24
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37281MAH–XXXSP,M37281MFH–XXXSP
M37281MKH–XXXSP,M37281EKSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
Fig. 8.3.4 Interrupt Control Register 1
b7b6 b5b4b3 b2b1b0
Interrupt control register 1 (ICON1) [Address 00FE
16]
B
0
Na
me
Interrupt Control Register 1
Timer 1 interrupt
enable bit (TM1E)
1 Timer 2 interrupt
enable bit (TM2E)
2 Timer 3 interrupt
enable bit (TM3E)
3
4 OSD interrupt enable bit
(OSDE)
7 Nothing is assigned. This bit is a write disable
bit. When this bit is read out, the value is “0.”
Timer 4 interrupt
enable bit (TM4E)
5V
SYNC interrupt enable
bit (VSCE)
6
A-D conversion • INT3 external
interrupt enable bit (ADE)
Functions
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enable
d
After reset
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
R —
RW
RW
Fig. 8.3.5 Interrupt Control Register 2
b7b6 b5b4b3 b2b1b0
Interrupt control register 2 (ICON2) [Address 00FF
16 ]
B
Name Functions
After reset
Interrupt Control Register 2
0
INT1 external interrupt enable
bit
(
IN1E
)
0 : Interrupt disabled
1 : Interrupt enabled
1
Data slicer interrupt
enable bit
(
DSE
)
2
Serial I/O interrupt
enable bit
(
SIOE
)
3
4
INT2 external interrupt enable
bit
(
IN2E
)
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
0
f(X IN )/4096 • SPRITE OSD
interrupt enable bit (CKE)
0 : Interrupt disabled
1 : Interrupt enabled
5
Multi-master I
2
C-BUS interface
interrupt enable bit (IICE)
0 : Interrupt disabled
1 : Interrupt enabled
0
6
Timer 5 • 6 interrupt
enable bit
(
TM56E
)
0 : Interrupt disabled
1 : Interrupt enabled
0
7
Timer 5 • 6 interrupt
switch bit
(
TM56S
)
0 : Timer 5
1 : Timer 6
0
RW
RW
RW
RW
RW
RW
RW
RW
RW