User`s manual

23
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
M37281MAH–XXXSP,M37281MFH–XXXSP
M37281MKH–XXXSP,M37281EKSP
Fig. 8.3.2 Interrupt Request Register 1
b7b6 b5b4b3 b2b1b0
Interrupt request register 1 (IREQ1) [Address 00FC
B Name
Interrupt Request Register 1
0
Timer 1 interrupt
re
q
uest bit
(
TM1R
)
1
Timer 2 interrupt
re
q
uest bit
(
TM2R
)
2
Timer 3 interrupt
re
q
uest bit
(
TM3R
)
3
Timer 4 interrupt
re
q
uest bit
(
TM4R
)
4
OSD interrupt request
bit
(
OSDR
)
5VSYNC interrupt
re
q
uest bit
(
VSCR
)
6
A-D conversion • INT3
external interrupt request
bit
(
ADR
)
7
✽ : “0” can be set by software, but “1” cannot be set.
16]
Functions
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
After reset
RW
0
0 ✽
0 ✽
0 ✽
✽
0 ✽
0 ✽
0 ✽
—
R
R
R
R
R
R
R
R
Nothing is assigned. This bit is a write disable bit.
When this bit is read out
,
the value is “0.”
0
Fig. 8.3.3 Interrupt Request Register 2
b7 b
6
b5b4b3 b2b1b0
Interrupt request register 2 (IREQ2) [Address 00FD
B
Name
Interrupt Request Register 2
0
INT1 external interrupt
re
q
uest bit
(
IN1R
)
1
Data slicer interrupt
re
q
uest bit
(
DSR
)
2
Serial I/O interrupt
re
q
uest bit
(
SIOR
)
3
4
INT2 external interrupt request
bit
(
IN2R
)
5
7
Fix this bit to “0.”
0
✽: “0” can be set by software, but “1” cannot be set.
16 ]
f(X IN )/4096 • SPRITE OSD
interru
p
t re
q
uest bit
(
CKR
)
Multi-master I
2
C-BUS interrupt
re
q
uest bit
(
IICR
)
6
Timer 5 • 6 interrupt
request bit (TM56R)
Functions
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
After reset
0
0
0
0
0
0
0
0
RW
✽
✽
✽
✽R
R
R
R
✽
R
R
✽
R
W
✽R