User`s manual

18
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37281MAH–XXXSP,M37281MFH–XXXSP
M37281MKH–XXXSP,M37281EKSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
Fig. 8.2.7 Memory Map of Special Function Register 2 (SFR2) (2)
2 3 0 1 6
2 3 1 1 6
232 16
2 3 3 1 6
2 3 4 1 6
235 16
2 3 6 1 6
2 3 7 1 6
238 16
2 3 9 1 6
2 3 A 1 6
2 3 B 1 6
23C 16
23D 16
2 3 E 1 6
2 3 F 1 6
2 2 0 1 6
221 16
2 2 2 1 6
2 2 3 1 6
2 2 4 1 6
225 16
226 16
2 2 7 1 6
2 2 8 1 6
229 16
2 2 B 1 6
22C 16
2 2 D 1 6
2 2 E 1 6
22F 16
22A 16
V e r t i c a l p o s i t i o n r e g i s t e r 1
1 1
( V P 1
1 1
)
Vertical position register 1
3
(VP1
3
)
Vertical position register 1
7
(VP1
7
)
V e r t i c a l p o s i t i o n r e g i s t e r 1
5
( V P 1
5
)
Vertical position register 1
6
(VP1
6
)
V e r t i c a l p o s i t i o n r e g i s t e r 1
1
( V P 1
1
)
Vertical position register 1
2
(VP1
2
)
V e r t i c a l p o s i t i o n r e g i s t e r 1
9
( V P 1
9
)
Vertical position register 1
10
(VP1
10
)
V e r t i c a l p o s i t i o n r e g i s t e r 1
4
( V P 1
4
)
V e r t i c a l p o s i t i o n r e g i s t e r 1
1 2
( V P 1
1 2
)
V e r t i c a l p o s i t i o n r e g i s t e r 1
8
( V P 1
8
)
V e r t i c a l p o s i t i o n r e g i s t e r 2
3
( V P 2
3
)
V e r t i c a l p o s i t i o n r e g i s t e r 2
7
( V P 2
7
)
Vertical position register 2
5
(VP2
5
)
V e r t i c a l p o s i t i o n r e g i s t e r 2
6
( V P 2
6
)
V e r t i c a l p o s i t i o n r e g i s t e r 2
1
( V P 2
1
)
V e r t i c a l p o s i t i o n r e g i s t e r 2
9
( V P 2
9
)
V e r t i c a l p o s i t i o n r e g i s t e r 2
1 0
( V P 2
1 0
)
V e r t i c a l p o s i t i o n r e g i s t e r 2
4
( V P 2
4
)
V e r t i c a l p o s i t i o n r e g i s t e r 2
1 2
( V P 2
1 2
)
V e r t i c a l p o s i t i o n r e g i s t e r 2
8
( V P 2
8
)
Vertical position register 2
2
(VP2
2
)
Vertical position register 2
11
(VP2
11
)
■ S F R 2 a r e a ( a d d r e s s e s 2 2 0 1 6 t o 2 3 F 1 6 )
A d d r e s sR e g i s t e
r
Bit allocation State immediately after rese
t
: F i x t o t h i s b i t t o “ 0 ”
( d o n o t w r i t e t o “ 1 ” )
:
< B i t a l l o c a t i o n >
<
State immediately after reset >
F u n c t i o n b i t
: No function bit
: F i x t o t h i s b i t t o “ 1 ”
( d o n o t w r i t e t o “ 0 ” )
N
ame
:
: “0” immediately after reset
: I n d e t e r m i n a t e i m m e d i a t e l y
a f t e r r e s e t
0
1
?
: “ 1 ” i m m e d i a t e l y a f t e r r e s e t
1
0
V e r t i c a l p o s i t i o n r e g i s t e r 2
1 4
( V P 2
1 4
)
V e r t i c a l p o s i t i o n r e g i s t e r 2
1 3
( V P 2
1 3
)
V e r t i c a l p o s i t i o n r e g i s t e r 2
1 6
( V P 2
1 6
)
V e r t i c a l p o s i t i o n r e g i s t e r 2
1 5
( V P 2
1 5
)
Vertical position register 1
13
(VP1
13
)
V e r t i c a l p o s i t i o n r e g i s t e r 1
1 4
( V P 1
1 4
)
Vertical position register 1
15
(VP1
15
)
Vertical position register 1
16
(VP1
16
)
b7 b0 b 7b 0
?
?
?
?
VP1
1
2VP1
1
3VP1
1
4VP1
1
5VP1
1
6VP1
1
7
VP1
2
2V P 1
2
3VP1
2
4VP1
2
5VP1
2
6VP1
2
7
VP1
3
2V P 1
3
3VP1
3
4VP1
3
5VP1
3
6VP1
3
7
VP1
4
2VP1
4
3VP1
4
4VP1
4
5VP1
4
6VP1
4
7
VP1
5
2V P 1
5
3VP1
5
4VP1
5
5VP1
5
6VP1
5
7
VP1
6
2V P 1
6
3VP1
6
4VP1
6
5VP1
6
6VP1
6
7
VP1
7
2VP1
7
3VP1
7
4VP1
7
5VP1
7
6VP1
7
7
VP1
8
2V P 1
8
3VP1
8
4VP1
8
5VP1
8
6VP1
8
7
VP1
9
2V P 1
9
3VP1
9
4VP1
9
5VP1
9
6VP1
9
7
VP1
10
2VP1
10
3VP1
10
4VP1
10
5VP1
10
6VP1
10
7
V
P 1
1 1
2VP1
11
3V P 1
1 1
4V P 1
1 1
5V P 1
1 1
6V P 1
1 1
7
VP1
1
1
VP1
2
1
VP1
3
1
VP1
4
1
VP1
5
1
VP1
6
1
VP1
7
1
VP1
8
1
VP1
9
1
VP1
10
1
V
P 1
1 1
1
V P 1
1 2
1V P 1
1 2
2VP1
12
3V P 1
1 2
4V P 1
1 2
5V P 1
1 2
6V P 1
1 2
7
V P 2
1
0V P 2
1
1
VP2
2
0V P 2
2
1
VP2
3
0VP2
3
1
V P 2
4
0V P 2
4
1
V P 2
5
0V P 2
5
1
V P 2
6
0V P 2
6
1
V P 2
7
0V P 2
7
1
V P 2
8
0V P 2
8
1
V P 2
9
0V P 2
9
1
VP2
10
0VP2
10
1
V P 2
1 1
0V P 2
1 1
1
V P 2
1 2
0V P 2
1 2
1
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
VP1
1
0
V
P 1
2
0
V
P 1
3
0
VP1
4
0
V
P 1
5
0
V
P 1
6
0
VP1
7
0
V
P 1
8
0
V
P 1
9
0
VP1
10
0
VP1
11
0
VP1
12
0
V
P 2
1 3
0V P 2
1 3
1
V
P 2
1 4
0V P 2
1 4
1
V
P 2
1 5
0V P 2
1 5
1
V P 2
1 6
0V P 2
1 6
1
V P 1
1 4
2VP1
14
3V P 1
1 4
4V P 1
1 4
5V P 1
1 4
6V P 1
1 4
7
V
P 1
1 5
2VP1
15
3V P 1
1 5
4V P 1
1 5
5V P 1
1 5
6V P 1
1 5
7
VP1
16
2VP1
16
3VP1
16
4VP1
16
5VP1
16
6VP1
16
7
VP1
14
0
VP1
15
0
VP1
16
0
V
P 1
1 4
1
V
P 1
1 5
1
VP1
16
1
VP1
13
1VP1
13
2VP1
13
3VP1
13
4VP1
13
5VP1
13
6VP1
13
7VP1
13
0