User`s manual
16
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37281MAH–XXXSP,M37281MFH–XXXSP
M37281MKH–XXXSP,M37281EKSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
Fig. 8.2.5 Memory Map of Special Function Register 1 (SFR2) (2)
F
0
1
6
F
1
1
6
F
2
1
6
F
3
1
6
F
4
1
6
F
5
1
6
F
6
1
6
F
7
1
6
F
8
1
6
F
9
1
6
F
A
1
6
F
B
1
6
F
C
1
6
F
D
1
6
F
E
1
6
F
F
1
6
E
0
1
6
E
1
1
6
E
2
1
6
E
3
1
6
E
4
1
6
E
5
1
6
E
6
1
6
E7
16
E
8
1
6
E
9
1
6
E
B
1
6
E
C
1
6
E
D
1
6
E
E
1
6
E
F
1
6
E
A
1
6
D
a
t
a
s
l
i
c
e
r
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
D
S
C
1
)
A
-
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
(
A
D
)
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
A
D
C
O
N
)
T
i
m
e
r
1
(
T
1
)
C
a
p
t
i
o
n
d
a
t
a
r
e
g
i
s
t
e
r
1
(
C
D
1
)
T
i
m
e
r
2
(
T
2
)
T
i
m
e
r
3
(
T
3
)
T
i
m
e
r
4
(
T
4
)
T
i
m
e
r
m
o
d
e
r
e
g
i
s
t
e
r
1
(
T
M
1
)
T
i
m
e
r
m
o
d
e
r
e
g
i
s
t
e
r
2
(
T
M
2
)
I
2
C
d
a
t
a
s
h
i
f
t
r
e
g
i
s
t
e
r
(
S
0
)
I
2
C
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
1
D
)
I
2
C
clock control register (S2)
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
1
(
I
R
E
Q
1
)
Interrupt request
register 2 (IREQ2)
I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
I
C
O
N
1
)
I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
(
I
C
O
N
2
)
C
P
U
m
o
d
e
r
e
g
i
s
t
e
r
(
C
M
)
D
a
t
a
s
l
i
c
e
r
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
(
D
S
C
2
)
I
2
C
status register (S1)
I
2
C
address register (S0D)
■
S
F
R
1
a
r
e
a
(
a
d
d
r
e
s
s
e
s
E
01
6
t
o
F
F1
6)
A
d
d
r
e
s
sR
e
g
i
s
t
e
r
Bit allocation State immediately after rese
t
:
F
i
x
t
o
t
h
i
s
b
i
t
t
o
“
0
”
(
d
o
n
o
t
w
r
i
t
e
t
o
“
1
”
)
:
<
B
i
t
a
l
l
o
c
a
t
i
o
n
>
<
State immediately after reset
>
Function bit
:
N
o
f
u
n
c
t
i
o
n
b
i
t
:
F
i
x
t
o
t
h
i
s
b
i
t
t
o
“
1
”
(
d
o
n
o
t
w
r
i
t
e
t
o
“
0
”
)
N
a
m
e
:
: “0” immediately after reset
: Indeterminate immediately
after reset
0
1
?
:
“
1
”
i
m
m
e
d
i
a
t
e
l
y
a
f
t
e
r
r
e
s
e
t
1
0
Caption data register 2 (CD2)
C
a
p
t
i
o
n
d
a
t
a
r
e
g
i
s
t
e
r
3
(
C
D
3
)
C
a
p
t
i
o
n
d
a
t
a
r
e
g
i
s
t
e
r
4
(
C
D
4
)
Caption Position register (CPS)
Data slicer test register 2
Data slicer test register 1
S
ync s
i
gna
l
counter reg
i
ster
(HC)
Cl
oc
k
run-
i
n
d
etect reg
i
ster
(CRD)
D
a
t
a
c
l
o
c
k
p
o
s
i
t
i
o
n
r
e
g
i
s
t
e
r
(
D
P
S
)
b7
b
0
b
7
b
0
TM20
TM21T
M
2
2T
M
2
3TM24
TM10
TM11T
M
1
2T
M
1
3TM14
CM2
TM1R
TM2RT
M
3
RT
M
4
ROSDRV
S
C
R
ADR
CK0
IN1R
DSR
SIOR
TM1E
TM2ET
M
3
ETM4EO
S
D
EV
S
C
E
I
N
1
ED
S
ES
I
O
EIN2E
T
M
2
5
FF
16
0
7
1
6
FF
16
0
7
1
6
T
M
1
5T
M
1
6TM17
T
M
2
6T
M
2
7
?
SAD0S
A
D
1S
A
D
2SAD3S
A
D
4SAD5S
A
D
6
RB
W
L
R
BA
D
0AASALPINBBT
R
XMST
BC0BC1BC2ESOALS
BSEL
0
BSEL
1
CCR0CCR1CCR2CCR3CCR4
AC
K
0
0
1
6
00
16
0
0
1
6
CK
R
IN2RIICR
T
M
5
6
R
ADE
CKEIICE
T
M
5
6
E
T
M
5
6
S
00
C
M
7CM5C
M
6
ADIN0ADIN1ADIN2
ADVREF
ADSTR
1
0
B
I
T
S
A
D
00
16
0
0
1
6
00
16
DSC10D
S
C
1
1D
S
C
1
2
D
S
C
2
0D
S
C
2
3D
S
C
2
4D
S
C
2
5
CRD3CRD4CRD5C
R
D
6CRD7
DPS3DPS4D
P
S
5D
P
S
6D
P
S
7
CPS0CPS3CPS4CPS5 CPS1CPS2CPS6CPS7
HC0HC3HC4HC5 HC1HC2
0?0? 0 ???
0
00
00
0
0
0
10
1
0
1
0
0
1
6
C
D
H
1
0C
D
H
1
3CDH14C
D
H
1
5 CDH11C
D
H
1
2C
D
H
1
6C
D
H
1
7
C
D
L
1
0C
D
L
1
3CDL14CDL15 CDL11CDL12C
D
L
1
6CDL17
00
16
0
0
1
6
00
16
0
0
1
6
00
16
00
16
00
16
0
0
1
6
00
16
D1D2D3D4D5D6D7 D0
00
00?00 0
0
0
0
01
0
0?
FAST
MODE
A
C
K
B
I
T
0
C
D
H
2
0C
D
H
2
3CDH24C
D
H
2
5 CDH21C
D
H
2
2C
D
H
2
6C
D
H
2
7
CDL20CDL23CDL24CDL25 CDL21CDL22CDL26CDL27
00
16
00
16
00
16
0
0
1
6
?
?
00
0?001 0
0
9
1
6
3
C
1
6
0
B
a
n
k
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
B
K
)
BK0B
K
3B
K
1B
K
2
BK6BK7
00
??
00??? ?