User`s manual

145
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
M37281MAH–XXXSP,M37281MFH–XXXSP
M37281MKH–XXXSP,M37281EKSP
Address 00EA16
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
C
l
o c
k
r u n -
i
n
d
e t e c t r e g
i
s t e r
(
C
R
D
)
[
A
d
d
r e s s 0 0
E
A
1 6
]
R
W
C
l
o c
k
R
u n -
i
n
D
e t e c t
R
e g
i
s t e
r
0
t o
2
0
R
—
T
est
bi
ts
3
t o
7
N
u m
b
e r o
f
r e
f
e r e n c e c
l
o c
k
s t o
b e c o u n t e d i n o n e c l o c k r u n - i n
p u l s e p e r i o d .
Cl
oc
k
run-
i
n
d
etect
i
on
bit(CRD3 to CRD7)
0
R
—
R
e a
d
- o n
l
y
B
A
f
t e r r e s e t
F
unct
i
on
s
N
a m e
Address 00E616
Address 00E916
b7 b6 b5 b4 b3 b2 b1 b0
Caption Position Register (CPS) [Address 00E6
16 ]
Caption Position Registe
r
0
to
4
0
R
W
0
R
W
Caption position
bits(CPS0 to CPS4)
6, 7 Refer to the corresponding
Table (Table 8.10.1).
Slice line mode
specification bits
(in 1 field) (CPS6, CPS7)
5 0: Data is not latched yet and a
clock-run-in is not determined.
1: Data is latched and a
clock-run-in is determined.
Caption data latch
completion flag 2
(CPS5)
Indeterminate
R
—
B After resetFunctionsNam
e
R
W
b7 b6 b5 b4 b3 b2 b1 b0
Sync pulse counter register (HC) [Address 00E9
16 ]
R
W
Sync Pulse Counter Registe
r
0
to
4
Indeterminate
R
—
6, 7 0
R
—
Count value (HC0 to HC4)
5
0
R
W
Count source (HC5) 0: H SYNC signal
1: Composite sync signal
B
After reset
FunctionsNam
e
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”