Technical information
52
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
_____
Before φ ONW input set up time
_____
After φ ONW input hold time
Before φ data bus set up time
After φ data bus hold time
___ _____
Before RD ONW input set up time
___
_____
Before WR ONW input set up time
___ _____
After RD ONW input hold time
___
_____
After WR ONW input hold time
___
Before RD data bus set up time
___
After RD data bus hold time
____
tsu(ONW–φ)
____
th(φ–ONW)
tsu(DB–φ)
th(φ–DB)
____
__
tsu
(ONW–RD)
____ ___
tsu
(ONW–WR)
__
____
th(RD–ONW)
___ ____
th(WR–ONW)
__
tsu(DB–RD)
__
th(RD–DB)
Symbol Parameter
Limits
Min.
ns
ns
ns
ns
ns
ns
ns
ns
Unit
–20
–20
120
0
–20
–20
120
0
Typ. Max.
φ clock cycle time
φ clock “H” pulse width
φ clock “L” pulse width
AD15–AD8 delay time
AD15–AD8 valid time
AD7–AD0 delay time
AD7–AD0 valid time
SYNC delay time
SYNC valid time
Data bus delay time
Data bus valid time
___
___
RD pulse width, WR pulse width
___
___
RD pulse width, WR pulse width
(when one-wait is valid)
___
After AD15–AD8 RD delay time
___
After AD15–AD8 WR delay time
___
After AD7–AD0 RD delay time
___
After AD7–AD0 WR delay time
___
After RD AD15–AD8 valid time
___
After WR AD15–AD8 valid time
___
After RD AD7–AD0 valid time
___
After WR AD7–AD0 valid time
___
After WR data bus delay time
___
After WR data bus valid time
_________
RESETOUT output delay time (Note 1)
_________
RESETOUT output valid time (Note 1)
100
100
80
80
300
150
Symbol Parameter
Limits
Min.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
tc(XIN)–20
tc(XIN)–20
5
5
10
tc(X
IN
)–20
3tc(X
IN
)–20
tc(X
IN
)–100
tc(XIN)–100
5
5
10
0
2tc(XIN)
40
10
50
10
40
10
30
t
c(X
IN
)
–40
t
c(X
IN
)
–50
10
10
30
Typ. Max.
tc(φ)
twH(φ)
twL(φ)
td(φ–AH)
tv(φ–AH)
td(φ–AL)
tv(φ–AL)
td(φ–SYNC)
tv(φ–SYNC)
td(φ–DB)
tv(φ–DB)
__
twL(RD)
___
twL(WR)
__
td(AH–RD)
___
td(AH–WR)
__
td(AL–RD)
___
td(AL–WR)
__
tv(RD–AH)
___
tv(WR–AH)
__
tv(RD–AL)
___
tv(WR–AL)
___
td(WR–DB)
___
tv(WR–DB)
___
_____
t
d
(RESET–RESET
OUT
)
_____
tv(φ–RESET)
Test conditions
Note 1:
_________
The RESETOUT output goes “H” in sync with the rise of the φ clock that is anywhere between about 8 cycle and 13 cycles after
______
the RESET input goes “H”.
Fig. 32
TIMING REQUIREMENTS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
SWITCHING CHARACTERISTICS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(High-Speed Version) (VCC = 2.7 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
60
60
Fig. 32 Circuit for measuring output switching
characteristics (1)
Fig. 33 Circuit for measuring output switching
characteristics (2)
Measurement output pin
100pF
CMOS output
100pF
N-channel open-drain output
1kΩ
Measurement output pin
(High-speed version)
(VCC = 2.7 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
MITSUBISHI MICROCOMPUTERS
3806 Group