Technical information

38
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
140
30
30
200
40
30
30
Symbol Parameter
Limits
Min.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
SWITCHING CHARACTERISTICS 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
t c(S CLK1 ) /2–30
t c(S CLK1 ) /2–30
–30
t c(S CLK2 ) /2–160
t c(S CLK2 ) /2–160
0
10
10
Typ. Max.
twH(SCLK1)
twL(SCLK1)
t d(S CLK1 –T X D)
t v(S CLK1 –T X D)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
t d(S CLK2 –S OUT2 )
t v(S CLK2 –S OUT2 )
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Test conditions
Fig. 32
Fig. 33
Fig. 32
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: Pins XOUT and P70–P77 are excluded.
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
350
50
50
400
50
50
50
Symbol Parameter
Limits
Min.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
SWITCHING CHARACTERISTICS 2 (VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
t c(S CLK1 ) /2–50
t c(S CLK1 ) /2–50
–30
t c(S CLK2 ) /2–240
t c(S CLK2 ) /2–240
0
20
20
Typ. Max.
twH(SCLK1)
twL(SCLK1)
t d(S CLK1 –T X D)
t v(S CLK1 –T X D)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
t d(S CLK2 –S OUT2 )
t v(S CLK2 –S OUT2 )
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Test conditions
Fig. 32
Fig. 33
Fig. 32
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: Pins XOUT and P70–P77 are excluded.
MITSUBISHI MICROCOMPUTERS
3806 Group