Technical information

57
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
140
30
30
0.2✕tC(SCLK2)
40
30
30
Symbol Parameter
Limits
Min.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted.)
t c(S CLK1 ) /2–30
t c(S CLK1 ) /2–30
–30
t c(S CLK2 ) /2–160
t c(S CLK2 ) /2–160
0
10
10
Typ. Max.
twH(SCLK1)
twL(SCLK1)
t d(S CLK1 –T X D)
t v(S CLK1 –T X D)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
t d(S CLK2 –S OUT2 )
t v(S CLK2 –S OUT2 )
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: X
OUT and XCOUT pins are excluded.
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
350
50
50
0.2✕t
C(SCLK2)
50
50
50
Symbol Parameter
Limits
Min.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, and VCC = 3.0 to 4.0 V, Ta = –40 to –20 °C, unless otherwise noted.)
t c(S CLK1 ) /2–50
t c(S CLK1 ) /2–50
–30
t c(S CLK2 ) /2–240
t c(S CLK2 ) /2–240
0
20
20
Max.
twH(SCLK1)
twL(SCLK1)
t d(S CLK1 –T X D)
t v(S CLK1 –T X D)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
t d(S CLK2 –S OUT2 )
t v(S CLK2 –S OUT2 )
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: X
OUT and XCOUT pins are excluded.
Typ.
SWITCHING CHARACTERISTICS 1 (Extended Operating Temperature Version)
SWITCHING CHARACTERISTICS 2 (Extended Operating Temperature Version)
Measurement output pin
100pF
CMOS output
Note: When bit 4 of the UART
control register (address 001B
16) is “1”.
(N-channel open-drain output mode)
Measurement output pin
100pF
N-channel open-drain output (Note)
1kΩ
Fig.40 Circuit for measuring output switching characteristics