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3886 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

C Data Shift Register (S0)] 001216

The I

C data shift register (S0 : address 001216) is an 8-bit shift

When transmit data is written into this register, it is transferred to

the outside from bit 7 in synchronization with the SCL clock, and

each time one-bit data is output, the data of this register are

shifted by one bit to the left. When data is received, it is input to

this register from bit 0 in synchronization with the SCL clock, and

each time one-bit data is input, the data of this register are shifted

by one bit to the left. The minimum 2 cycles of

are required from

the rising of the SCL clock until input to this register.

The I

C data shift register is in a write enable status only when the

C-BUS interface enable bit (ES0 bit : bit 3 of address 1516) of

the I

C control register is “1.” The bit counter is reset by a write in-

struction to the I

C data shift register. When both the ES0 bit and

the MST bit of the I

C status register (address 001416) are “1,” the

SCL is output by a write instruction to the I

C data shift register.

Reading data from the I

C data shift register is always enabled re-

gardless of the ES0 bit value.

C Address Register (S0D)] 001316

The I

C address register (address 001316) consists of a 7-bit slave

address and a read/write bit. In the addressing mode, the slave ad-

dress written in this register is compared with the address data to be

received immediately after the START condition is detected.

•Bit 0: Read/write bit (RBW)

This is not used in the 7-bit addressing mode. In the 10-bit ad-

dressing mode, the first address data to be received is compared

with the contents (SAD6 to SAD0 + RBW) of the I

C address reg-

ister.

The RBW bit is cleared to “0” automatically when the stop condi-

tion is detected.

•Bits 1 to 7: Slave address (SAD0–SAD6)

These bits store slave addresses. Regardless of the 7-bit address-

ing mode and the 10-bit addressing mode, the address data

transmitted from the master is compared with the contents of

these bits.

Fig. 36 Structure of I

C address register

(

)

7b0