Technical information
97
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Table 42 Switching characteristics 1
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tV (SCLK1-TXD)
tr (SCLK1)
tf (SCLK1)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tV (SCLK2-SOUT2)
tf (SCLK2)
tr (CMOS)
tf (CMOS)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
tC(SCLK1)/2–30
tC(SCLK1)/2–30
–30
tC(SCLK2)/2–160
tC(SCLK2)/2–160
0
Typ.
10
10
Max.
140
30
30
200
30
30
30
Symbol Unit
Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: The X
OUT pin is excluded.
Test
conditions
Fig. 83
Fig. 84
Fig. 83
Table 43 Switching characteristics 2
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tV (SCLK1-TXD)
tr (SCLK1)
tf (SCLK1)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tV (SCLK2-SOUT2)
tf (SCLK2)
tr (CMOS)
tf (CMOS)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
tC(SCLK1)/2–50
tC(SCLK1)/2–50
–30
tC(SCLK2)/2–240
tC(SCLK2)/2–240
0
Typ.
20
20
Max.
350
50
50
400
50
50
50
Symbol Unit
Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: The X
OUT pin is excluded.
Test
conditions
Fig. 83
Fig. 84
Fig. 83