Technical information

2-25
3800 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
Fig. 2.3.4 Structure of Serial I/O control register
Fig. 2.3.5 Structure of UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register (UARTCON) [Address : 1B
16 ]
UART control register
0
0
0
0
0
1

Character length
selection bit (CHAS)
0 : 8 bits
1 : 7 bits
Parity enable bit
(PARE)
0 :
Parity checking disabled
1 : Parity checking enabled
Stop bit length selection
bit (STPS)
0 : 1 stop bit
1 : 2 stop bits
P4
5 /TxD P-channel
output disable bit
(POFF)
Nothing is allocated for these bits. These are write
disabled bits. When these bits are read out, the
values are “1.”
Parity selection bit
(PARS)
0 : Even parity
1 : Odd parity
1

1

At reset
B
Name Function
RW
0
1
2
3
4
5
6
7
In output mode
1 : N-channel open-drain
output
0 : CMOS output
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O control register
0
0
0
0
0 : Transmit buffer empty
1 : Transmit shift operating
completion
0 : f(X IN )
1 : f(X
IN )/4
Serial I/O synchronous clock
selection bit (SCS)
At selecting clock synchronous serial I/O
0 : BRG output divided by 4
1 : External clock input
At selecting UART
0 : BRG output divided by 16
1 : External clock input divided by 16
Transmit interrupt
source selection bit
(TIC)
SRDY output enable bit
(SRDY)
0 : I/O port (P47)
1 :
S RDY output pin
At reset
B
Name Function
RW
0
1
2
3
0
0
0 : Transmit disabled
1 : Transmit enabled
Transmit enable bit (TE)
Receive enable bit (RE)
0 : Receive disabled
1 : Receive enabled
4
5
0
0
Serial I/O enable bit
(SIOE)
Serial I/O mode
selection bit (SIOM)
0 : UART
1 : Clock synchronous serial I/O
0 : Serial I/O disabled
(P4
4 –P4 7 : I/O port)
1 : Serial I/O enabled
(P4
4 –P4 7 : Serial I/O function pin)
6
7
BRG count source
selection bit (CSS)
Serial I/O control register (SIOCON) [Address : 1A16]