Technical information
APPLICATION
2.2 Timer
2-21
3800 GROUP USER’S MANUAL
Fig. 2.2.21 Setting of related registers [Measurement of pulse width]
01
CNTR
0
active edge switch bit : Count “H” level width
Timer X operating mode bits : Pulse width measurement mode
Timer X count stop bit : Count stop
Set to “0” at starting to count.
TM
Timer XY mode register (Address : 23
16
)
b7 b0
11
255
PREX
Prescaler X (Address : 24
16
)
Set “division ratio – 1”
255
TX
Timer X (Address : 25
16
)
1
Timer X interrupt enable bit : Interrupt enabled
ICON1
Interrupt control register 1 (Address : 3E
16
)
b7 b0
b7 b0
b7 b0
1
CNTR
0
interrupt enable bit : Interrupt enabled
ICON2
Interrupt control register 2 (Address : 3F
16
)
0
CNTR
0
interrupt request bit
(This bit is set to “1” at completion of inputting
“H” level signal.)
IREQ2
Interrupt request register 2 (Address : 3D
16
)
b7 b0
b7 b0
Timer X interrupt request bit
(This bit is set to “1” at underflow of Timer X.)
IREQ1
Interrupt request register (Address : 3C
16
)
0
b7 b0