Technical information

1-34
HARDWARE
3800 GROUP USER’S MANUAL
FUNCTIONAL DESCRIPTION SUPPLEMENT
Timing After Interrupt
The interrupt processing routine begins with the machine cycle fol-
lowing the completion of the instruction that is currently in execu-
tion.
Figure 32 shows a timing chart after an interrupt occurs, and Fig-
ure 33 shows the time up to execution of the interrupt processing
routine.
Fig. 32 Timing chart after an interrupt occurs
Fig. 33 Time up to execution of the interrupt processing routine
: CPU operation code fetch cycle
: Vector address of each interrupt
: Jump destination address of each interrupt
: “00
16 ” or “01 16 ”
SYNC
B
L , B H
A L , A H
SPS
φ
Data bus
Not used PC H PC L PS A L A H
Address bus S , SPS S-2 , SPSS-1, SPS PC B L B H A L , A H
SYNC
RD
WR
Interrupt processing routine
Generation of interrupt request
Main routine
7 to 23 cycles
(At performing 8.0 MHz, 1.75 µs to 5.75 µs)
2 cycles 5 cycles
Start of interrupt processing
0 to 16 cycles
Waiting time for
post-processing
of pipeline
Stack push and
Vector fetch
✻ : at execution of DIV instruction (16 cycles)
✻