Technical information

HARDWARE
1-21
3800 GROUP USER’S MANUAL
Fig. 16 Block diagram of timer X, timer Y, timer 1, and timer 2
FUNCTIONAL DESCRIPTION
Timer X latch (8)
Timer X (8)
Prescaler X latch (8)
Prescaler X (8)
Oscillator Divider
f(X
IN) 1/16
CNTR
0 active
edge switch bit
P54/CNTR0 pin
Port P5
4
direction register
“0”
“1”
Event
counter
mode
Timer X count stop bit
CNTR
0 active
edge switch
bit
Port P5
4
latch
Pulse output
mode
Pulse width
measurement
mode
Timer mode
Pulse output
mode
“1”
“0”
Timer X latch write pulse
Pulse output mode
To timer X interrupt
request bit
To CNTR
0 interrupt
request bit
Data bus
Timer Y latch (8)
Timer Y (8)
Prescaler Y latch (8)
Prescaler Y (8)
CNTR1 active
edge switch bit
P55/CNTR1 pin
Port P5
5
direction register
“0”
“1”
Event
counter
mode
Timer Y count stop bit
CNTR
1 active
edge switch
bit
Port P5
5
latch
Pulse output
mode
Pulse width
measurement
mode
Timer mode
Pulse output
mode
“1”
“0”
Timer Y latch write pulse
Pulse output mode
To timer Y interrupt
request bit
To CNTR
1 interrupt
request bit
Data bus
Q
Q
R
Toggle flip- flop T
Q
Q
R
Toggle flip- flop T
Timer 2 latch (8) Timer 1 latch (8)
Prescaler
12 latch (8)
Prescaler 12 (8)
Timer 2 (8)Timer 1 (8)
Data bus
To timer 2 interrupt
request bit
To timer 1 interrupt
request bit