Technical information

HARDWARE
1-11
3800 GROUP USER’S MANUAL
Fig. 8 Register push and pop at interrupt generation and subroutine call
Table 4. Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
Push instruction to stack
PHA
PHP
Pop instruction from stack
PLA
PLP
FUNCTIONAL DESCRIPTION
On-going Routine
Execute JSR
M(S) ← (PCH)
(S) ← (S – 1)
M(S) ← (PCL)
(S) ← (S – 1)
Subroutine
(S) ← (S + 1)
(PCL) ← M(S)
(S) ← (S + 1)
(PCH) ← M(S)
Execute RTS
(S) ← (S – 1)
M(S) ← (PS)
(S) ← (S – 1)
Interrupt
Service Routine
(S) ← (S + 1)
(PS) ← M(S)
(S) ← (S + 1)
(PCL) ← M(S)
Execute RTI
(S) ← (S + 1)
(PCH) ← M(S)
M(S) ← (PCH)
(S) ← (S – 1)
M(S) ← (PCL)
Interrupt Request
(Note 1)
Store Return Address
on Stack (Note 2)
Restore Return
Address
Restore Contents of
Processor Status
Register
I Flag “0” to “1”
Fetch the Jump
Vector
Store Contents of
Processor Status
Register on Stack
Store Return Address
on Stack (Note 2)
Notes 1 : The condition to enable the interrupt → Interrupt enable bit is “1”
Interrupt disable flag is “0”
2 : When an interrupt occurs, the address of the next instruction to be executed is stored in
the stack area. When a subroutine is called, the address one before the next instruction
to be executed is stored in the stack area.
Restore Return
Address