Technical information
HARDWARE
1-5
3800 GROUP USER’S MANUAL
• 8-bit CMOS I/O port with the same function as
port P0
• CMOS compatible input level
• CMOS 3-state output structure
Pin
VCC
VSS
CNVSS
RESET
XIN
XOUT
P00 – P07
P10 – P17
P20 – P27
P30 – P37
P40, P41
P42/INT0,
P43/INT1
P44/RXD,
P45/TXD,
P46/SCLK,
P47/SRDY
P50/INT2 –
P53/INT5
P54/CNTR0,
P55/CNTR1
P56, P57
P60 – P67
P70, P71
Function
• Apply voltage of 3.0 V to 5.5 V to VCC, and 0 V to VSS.
(Extended operating temperature version : 4.0 V to 5.5 V)
• This pin controls the operation mode of the chip.
• Normally connected to VSS.
• If this pin is connected to VCC, the internal ROM is inhibited and external memory is accessed.
• Reset input pin for active “L”
• Input and output signals for the internal clock generating circuit.
• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the
oscillation frequency.
• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• The clock is used as the oscillating source of system clock.
• 8 bit CMOS I/O port
• I/O direction register allows each pin to be individually programmed as either input or output.
• At reset this port is set to input mode.
• In modes other than single-chip, these pins are used as address, data, and control bus I/O pins.
• CMOS compatible input level
• CMOS 3-state output structure
• 8-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
• CMOS 3-state output structure
PIN DESCRIPTION
Table 1. Pin description
PIN DESCRIPTION
Name
Power source
CNVSS
Reset input
Clock input
Clock output
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
I/O port P5
I/O port P6
I/O port P7
Function except a port function
• External interrupt input pins
• Serial I/O I/O pins
• External interrupt input pins
• Timer X and Timer Y I/O pins
• 8-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
• CMOS 3-state output structure
• 2-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
• CMOS 3-state output structure