Technical information

3800 GROUP USER’S MANUAL
3-36
APPENDIX
3.5 List of registers
Fig. 3.5.16 Structure of Interrupt control register 1
Fig. 3.5.17 Structure of Interrupt control register 2
Timer Y interrupt enable bit
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
B
Function
At reset
RW
0
1
2
3
0
0
0
0
Interrupt control register 1 (ICON1) [Address : 3E16]
Name
INT0 interrupt enable bit
INT
1 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
4
5
6
7
0
0
0
0
Timer X interrupt enable bit
Timer 1 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Timer 2 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O transmit interrupt
enable bit
Serial I/O receive interrupt
enable bit
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
B
Function
At reset
RW
0
1
2
3
0
0
0
0
Interrupt control reigster 2 (ICON2) [Address : 3F16]
Name
CNTR0 interrupt enable bit
CNTR
1 interrupt enable bit
INT
2 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
INT
3 interrupt enable bit
5
6
0
0 : Interrupt disabled
1 : Interrupt enabled
Fix these bits to “0.”
INT
5 interrupt enable bit
4
0
0 : Interrupt disabled
1 : Interrupt enabled
INT4 interrupt enable bit
0
0 0
7
0