Technical information

3800 GROUP USER’S MANUAL
3-35
APPENDIX
3.5 List of registers
Fig. 3.5.14 Structure of Interrupt request register 1
Fig. 3.5.15 Structure of Interrupt request register 2
✻
0 : No interrupt request
1 : Interrupt request
Serial I/O receive interrupt
request bit
Serial I/O transmit interrupt
request bit
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
B
Function
At reset RW
Interrupt request reigster 1 (IREQ1) [Address : 3C16]
Name
✻
“0” is set by software, but not “1.”
Timer Y interrupt request
bit
4
5
6
7
0
0
0
0
Timer X interrupt request
bit
Timer 1 interrupt request bit
0 : No interrupt request
1 : Interrupt request
Timer 2 interrupt request bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
✻
✻
✻
✻
✻
✻
✻
0
0
0
0
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
INT
0 interrupt request bit
INT
1 interrupt request bit
0
1
2
3
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
B
Function
At reset
RW
0
1
2
3
0
0
0
0
Interrupt request reigster 2 (IREQ2) [Address : 3D16]
Name
CNTR0 interrupt request bit
CNTR
1 interrupt request bit
INT
2 interrupt request bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
INT
3 interrupt request bit
✻
✻
✻
✻
5
6
0
0 : No interrupt request
1 : Interrupt request
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0.”
INT
5 interrupt request bit
✻
✻ “0” is set by software, but not “1.”
4
0
0 : No interrupt request
1 : Interrupt request
INT
4 interrupt request bit
✻
0
7
0
✕
✕