Technical information

3800 GROUP USER’S MANUAL
3-34
APPENDIX
3.5 List of registers
Fig. 3.5.12 Structure of Interrupt edge selection register
Fig. 3.5.13 Structure of CPU mode register
✕
✕
✕
✕
3
2
0
1
CPU mode register (CPUM) [Adress : 3B16]
Nothing is allocated for these bits. These are write
disabled bits. When these bits are read out, the
values are “0.”
0
0
0
0
0
CPU mode register
Processor mode bits
00 : Single-chip mode
01 : Memory expansion mode
10 : Microprocessor mode
11 : Not available
Stack page selection
bit
0 : 0 page
1 : 1 page
0
0
✕
✕
✻ An initial value of bit 1 is determined by a level of the CNV
SS pin.
✻
At reset
B
Name Function
RW
4
5
6
7
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A16]
Interrupt edge selection register
INT0 interrupt edge
selection bit
0 : Falling edge active
1 : Rising edge active
0
INT1 interrupt edge
selection bit
0 : Falling edge active
1 : Rising edge active
INT
3 interrupt edge
selection bit
0 : Falling edge active
1 : Rising edge active
Nothing is allocated for these bits. These are write disabled
bits. When these bits are read out, the values are “0.”
0
INT4 interrupt edge
selection bit
0 : Falling edge active
1 : Rising edge active
INT
5 interrupt edge
selection bit
0 : Falling edge active
1 : Rising edge active
0
✕
0
0
0
0
0
INT2 interrupt edge
selection bit
0 : Falling edge active
1 : Rising edge active
At reset
B
Name Function
RW
0
1
2
3
4
5
6
7
✕
b7 b6 b5 b4 b3 b2 b1 b0