Technical information

3800 GROUP USER’S MANUAL
APPENDIX
3.1 Electrical characteristics
3-10
3.1.8 Timing requirements and Switching characteristics (Extended operating temperature version)
Note: Bit 6 of address 001A16 is “1”. Divide this value by four bit 6 of address 001A16 is “0”.
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR
0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT5 input “H” pulse width
INT0 to INT5 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
tW(RESET)
tc(XIN)
tWH(XIN)
tWL(XIN)
tc(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tc(SCLK)
tWH(SCLK)
tWL(SCLK)
t su(R X D–S CLK )
t h(S CLK –R X D)
Symbol Parameter
Limits
Min.
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
2
125
50
50
200
80
80
80
80
800
370
370
220
100
Typ. Max.
Table 3.1.15 Timing requirements (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rise time
Serial I/O clock output fall time
CMOS output rise time (Note 2)
CMOS output fall time (Note 2)
140
30
30
30
30
Symbol Parameter
Limits
Min.
ns
ns
ns
ns
ns
ns
ns
ns
Unit
t c(S CLK ) /2–30
t c(S CLK ) /2–30
–30
10
10
Typ. Max.
tWH(SCLK)
tWL(SCLK)
t d(S CLK –T X D)
t v(S CLK –T X D)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Test conditions
Fig. 3.1.1
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT pin is excluded.
Table 3.1.16 Switching characteristics (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)