Technical information

3-5
3800 GROUP USER’S MANUAL
APPENDIX
3.1 Electrical characteristics
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
140
30
30
30
30
Symbol Parameter
Limits
Min.
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Table 3.1.6 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
t c(S CLK ) /2–30
t c(S CLK ) /2–30
–30
10
10
Typ. Max.
tWH(SCLK)
tWL(SCLK)
t d(S CLK –T X D)
t v(S CLK –T X D)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Test conditions
Fig. 3.1.1
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT pin is excluded.
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
350
50
50
50
50
Symbol Parameter
Limits
Min.
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Table 3.1.7 Switching characteristics (2) (VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
t c(S CLK ) /2–50
t c(S CLK ) /2–50
–30
20
20
Typ. Max.
tWH(SCLK)
tWL(SCLK)
t d(S CLK –T X D)
t v(S CLK –T X D)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Test conditions
Fig. 3.1.1
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT pin is excluded.