Technical information

APPLICATION
2.4 Processor mode
2-52
3800 GROUP USER’S MANUAL
Fig. 2.4.6 Write-cycle (W control, SRAM)
td(AH—WR)
W
(WR of 3800)
65 ns (max)
35 ns (min)
Address (low-order)
Address (high-order)
Data
DQ
1 –DQ 8
(Port P2)
S
(A15)
OE
(RD of 3800)
“ H ” level
125 ns - 10 ns (min)
125 ns - 35 ns (min)
td(AH—WR)
t
WL (WR)
td(WR—DB)
tsu(D)
: WR delay time after outputting address of 3800
: WR pulse width of 3800
t WL (WR)
: Data bus delay time after WR of 3800
td(WR—DB)
: Data setup time of M5M5256BP
tsu(D)
A 0 –A 7
(Port P0)
A 8 –A 14
(Port P1)