Technical information

APPLICATION
2.4 Processor mode
2-49
3800 GROUP USER’S MANUAL
2.4 Processor mode
2.4.1 Memory map of processor mode
Fig. 2.4.1 Memory map of processor mode related register
2.4.2 Related register
Fig. 2.4.2 Structure of CPU mode register
003B16
CPU mode register (CPUM)
✕
✕
✕
✕
3
2
0
1
CPU mode register (CPUM) [Adress : 3B 16 ]
Nothing is allocated for these bits. These are write
disabled bits. When these bits are read out, the
values are “0.”
0
0
0
0
0
CPU mode register
Processor mode bits
00 : Single-chip mode
01 : Memory expansion mode
10 : Microprocessor mode
11 : Not available
Stack page selection
bit
0 : 0 page
1 : 1 page
0
0
✕
✕
✻ An initial value of bit 1 is determined by a level of the CNV
SS pin.
✻
At reset
B
Name Function
RW
4
5
6
7
b7 b6 b5 b4 b3 b2 b1 b0