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Old Company Name in Catalogs and Other Documents

On April 1

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both

companies. Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

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April 1

, 2010

Renesas Electronics Corporation

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Summary of content (175 pages)

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To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
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Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
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To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.
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User’s Manual 8 3800 Group User’s Manual MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES New publication, 1996.
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Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
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Preface This user’s manual describes Mitsubishi’s CMOS 8bit microcomputers 3800 Group. After reading this manual, the user should have a through knowledge of the functions and features of the 3800 Group, and should be able to fully utilize the product. The manual starts with specifications and ends with application examples. For details of software, refer to the “SERIES MELPS 740 USER’S MANUAL.
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BEFORE USING THIS USER’S MANUAL This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. Chapter 3 also includes necessary information for systems development. Be sure to refer to this chapter. 1. Organization ● CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function.
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LIST OF GROUPS HAVING THE SIMILAR FUNCTIONS 3800 group, one of the CMOS 8-bit microcomputer 38000 series presented in this user’s manual is provided with standard functions. The basic functions of the 3800, 3802, 3806 and 3807 groups having the same functions are shown below. For the detailed functions of each group, refer to the related data book and user’s manual.
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Table of contents Table of contents CHAPTER 1. HARDWARE DESCRIPTION ................................................................................................................................ 1-2 FEATURES ...................................................................................................................................... 1-2 APPLICATIONS ..............................................................................................................................
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Table of contents CHAPTER 2. APPLICATION 2.1 I/O port ..................................................................................................................................... 2.1.1 Memory map of I/O port ............................................................................................... 2.1.2 Related registers ............................................................................................................ 2.1.3 Handling of unused pins ....................................
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Table of contents 3.3.5 Notes on memory expansion mode and microprocessor mode ............................ 3-21 3.3.6 Notes on built-in PROM .............................................................................................. 3-22 3.4 Countermeasures against noise ...................................................................................... 3-24 3.4.1 Shortest wiring length .................................................................................................. 3-24 3.4.
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List of figures List of figures CHAPTER 1 HARDWARE Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 1 Pin configuration of M38002M4-XXXFP/M38003M6-XXXHP ....................................... 1-2 2 Pin configuration of M38002M4-XXXSP ......................................................................... 1-3 3 Functional block diagram ......................................................
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List of figures Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.2.7 Structure of Interrupt request register 2 ................................................................... 2-9 2.2.8 Structure of Interrupt control register 1 .................................................................. 2-10 2.2.9 Structure of Interrupt control register 2 .................................................................. 2-10 2.2.
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List of figures Fig. Fig. Fig. Fig. 2.3.31 2.3.32 2.3.33 2.3.34 Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 Setting of related registers at a transmitting side [Communication using UART] ........................ 2-45 Setting of related registers at a receiving side [Communication using UART] ............................ 2-46 Control procedure at a transmitting side [Communication using UART] .........
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List of figures CHAPTER 3 APPENDIX Fig. Fig. Fig. Fig. 3.1.1 3.1.2 3.1.3 3.1.4 Circuit Timing Timing Timing for measuring output switching characteristics ......................................... 3-11 diagram (in single-chip mode) .................................................................... 3-12 diagram (in memory expansion mode and microprocessor mode) (1) 3-13 diagram (in memory expansion mode and microprocessor mode) (2) 3-14 Fig. Fig. Fig. Fig. Fig. Fig. 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.
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List of tables List of tables CHAPTER 1 HARDWARE Table Table Table Table Table Table Table Table Table Table 1 Pin description ................................................................................................................. 1-5 2 List of supported products ............................................................................................. 1-8 3 List of supported products (Extended operating temperature version) ..................
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List of tables Table 3.3.1 Programming adapter ............................................................................................. 3-22 Table 3.3.2 Setting of programming adapter switch ............................................................... 3-22 Table 3.3.3 Setting of PROM programmer address ................................................................ 3-23 Table 3.5.1 Function of CNTR0 /CNTR 1 edge switch bit ........................................................
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CHAPTER 1 HARDWARE DESCRIPTION FEATURES APPLICATIONS PIN CONFIGURATION FUNCTIONAL BLOCK PIN DESCRIPTION PART NUMBERING GROUP EXPANSION FUNCTIONAL DESCRIPTION NOTES ON PROGRAMMING DATA REQUIRED FOR MASK ORDERS ROM PROGRAMMING METHOD FUNCTIONAL DESCRIPTION SUPPLEMENT
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HARDWARE DESCRIPTION/FEATURES/APPLICATIONS/PIN CONFIGURATION DESCRIPTION • Power source voltage ..................................................3.0 to 5.5 V The 3800 group is the 8-bit microcomputer based on the 740 family core technology. The 3800 group is designed for office automation equipment, household appliances and include four timers, serial I/O function. The various microcomputers in the 3800 group include variations of internal memory size and packaging.
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HARDWARE PIN CONFIGURATION PIN CONFIGURATION (TOP VIEW) 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 14 15 16 17 18 19 20 M38002M4-XXXSP VCC P71 P70 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55/CNTR 1 P54/CNTR 0 P53/INT 5 P52/INT 4 P51/INT 3 P50/INT 2 P47/SRDY P46/SCLK P45/TXD P44/RXD P43/INT 1 P42/INT 0 CNV SS RESET P41 P40 XIN XOUT VSS 52 51 50 49 48 47 46 45 21 44 22 43 23 42 24 41 25 40 26 39 27 38 28 37 29 36 30 35 31 34 32 33 P30
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1-4 31 Clock output XOUT Fig.
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HARDWARE PIN DESCRIPTION PIN DESCRIPTION Table 1. Pin description Pin Name Function Function except a port function VCC Power source • Apply voltage of 3.0 V to 5.5 V to VCC, and 0 V to VSS. (Extended operating temperature version : 4.0 V to 5.5 V) CNV SS CNVSS • This pin controls the operation mode of the chip. • Normally connected to VSS . • If this pin is connected to VCC, the internal ROM is inhibited and external memory is accessed.
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HARDWARE PART NUMBERING PART NUMBERING Product M3800 2 M 4 - XXX SP Package type SP : 64P4B package FP : 64P6N-A package HP : 64P6D-A package SS : 64S1B package FS : 64D0 package ROM number Omitted in some types.
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HARDWARE GROUP EXPANSION GROUP EXPANSION (2) Packages 64P4B ............................................ Shrink plastic molded DIP 64P6N-A ............................. 0.8 mm pitch plastic molded QFP 64P6D-A ............................. 0.5 mm pitch plastic molded QFP 64S1B ......................... Shrink ceramic DIP (EPROM version) 64D0 ................ 0.
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HARDWARE GROUP EXPANSION Currently supported products are listed below. Table 2.
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HARDWARE GROUP EXPANSION GROUP EXPANSION (EXTENDED OPERATING TEMPERATURE VERSION) Mitsubishi plans to expand the 3800 group (extended operating temperature version) as follows: (1) Support for mask ROM, One Time PROM, and EPROM versions ROM/PROM capacity ................................... 8 K to 32 K bytes RAM capacity ................................................ 384 to 640 bytes (2) Packages 64P4B ............................................ Shrink Plastic molded DIP 64P6N-A .........................
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HARDWARE FUNCTIONAL DESCRIPTION FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) Stack pointer (S) The 3800 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 User’s Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used.
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HARDWARE FUNCTIONAL DESCRIPTION On-going Routine Interrupt Request (Note 1) M(S) ← (PCH) Execute JSR (S) ← (S – 1) M(S) ← (PCH) Store Return Address on Stack (Note 2) M(S) ← (PCL) (S) ← (S – 1) (S) ← (S – 1) M(S) ← (PC L) M(S) ← (PS) (S) ← (S – 1) (S) ← (S – 1) Subroutine Store Contents of Processor Status Register on Stack Interrupt Service Routine Execute RTS Restore Return Address Store Return Address on Stack (Note 2) I Flag “0” to “1” Fetch the Jump Vector Execute RTI (S) ← (S + 1)
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HARDWARE FUNCTIONAL DESCRIPTION Processor status register (PS) The processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. After reset, the Interrupt disable (I) flag is set to “1”, but all other flags are undefined.
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HARDWARE FUNCTIONAL DESCRIPTION CPU mode register The CPU mode register is allocated at address 003B16 . The CPU mode register contains the stack page selection bit. b7 b0 CPU mode register (CPUM : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Not available Stack page selection bit 0 : 0 page 1 : 1 page Not used (return “0” when read) Fig.
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HARDWARE FUNCTIONAL DESCRIPTION Memory Special function register (SFR) area Zero page The Special Function Register area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. The 256 bytes from addresses 0000 16 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area.
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HARDWARE FUNCTIONAL DESCRIPTION 000016 Port P0 (P0) 002016 Prescaler 12 (PRE12) 000116 Port P0 direction register (P0D) 002116 Timer 1 (T1) 000216 Port P1 (P1) 002216 Timer 2 (T2) 000316 Port P1 direction register (P1D) 002316 Timer XY mode register (TM) 000416 Port P2 (P2) 002416 Prescaler X (PREX) 000516 Port P2 direction register (P2D) 002516 Timer X (TX) 000616 Port P3 (P3) 002616 Prescaler Y (PREY) 000716 Port P3 direction register (P3D) 002716 Timer Y (TY) 000816 Port
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HARDWARE FUNCTIONAL DESCRIPTION I/O Ports Direction registers The 3800 group has 58 programmable I/O pins arranged in eight I/O ports (ports P0 to P7). The I/O ports have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin becomes an input pin.
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HARDWARE FUNCTIONAL DESCRIPTION (1) Ports P0, P1, P2, P3, P40, P41, P56, P57, P6, P7 (2) Ports P42, P43, P50 – P53 Direction register Direction register Port latch Data bus Port latch Data bus Interrupt input (3) Port P44 (4) Port P45 Serial I/O enable bit Receive enable bit P45/TXD P-channel output disable bit Serial I/O enable bit Transmit enable bit Direction register Direction register Port latch Data bus Port latch Data bus Serial I/O input Serial I/O output (5) Port P46 (6) Port
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HARDWARE FUNCTIONAL DESCRIPTION Interrupts Interrupt operation Interrupts occur by fifteen sources: eight external, six internal, and one software. When an interrupt is received, the contents of the program counter and processor status register are automatically stored into the stack. The interrupt disable flag is set to inhibit other interrupts from interfering.
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HARDWARE FUNCTIONAL DESCRIPTION Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request Fig.
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HARDWARE FUNCTIONAL DESCRIPTION Timers Timer 1 and Timer 2 The 3800 group has four timers: timer X, timer Y, timer 1, and timer 2. All timers are count down. When the timer reaches “0016”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”.
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HARDWARE FUNCTIONAL DESCRIPTION Data bus Oscillator Divider f(XIN ) 1/16 Pulse width measurement mode P54/CNTR0 pin CNTR0 active edge switch bit “0” Timer X latch (8) Prescaler X (8) Timer X (8) Event counter mode Timer X count stop bit CNTR0 active edge switch bit Q “1” “0” Port P5 4 latch Toggle flip- flop Q Timer X latch write pulse Pulse output mode Data bus Pulse width measurement mode CNTR1 active edge switch bit “0” Prescaler Y latch (8) Timer Y latch (8) Prescaler Y (8) Timer Y
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HARDWARE FUNCTIONAL DESCRIPTION Serial I/O Clock synchronous serial I/O mode Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. Clock synchronous serial I/O mode can be selected by setting the mode selection bit of the serial I/O control register to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock.
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HARDWARE FUNCTIONAL DESCRIPTION Asynchronous serial I/O (UART) mode two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer can hold a character while the next character is being received.
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HARDWARE FUNCTIONAL DESCRIPTION Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD TBE=0 TSC=1✽ TBE=1 ST D0 D1 SP ST D0 Receive buffer read signal SP D1 ✽ 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) Generated at 2nd bit in 2-stop-bit mode RBF=0 RBF=1 Serial input RXD ST D0 D1 SP RBF=1 ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception).
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HARDWARE FUNCTIONAL DESCRIPTION b7 b0 b7 Serial I/O status register (SIOSTS : address 001916) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed SRDY output enable bit (SRDY) 0: P4 7 pin operates as ordinaly I/O pin 1: P4 7 pin operates as S RDY output pin Overrun error flag (OE) 0: No error 1: Overrun error Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has em
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HARDWARE FUNCTIONAL DESCRIPTION Reset Circuit To reset the microcomputer, the RESET pin should be held at an “L” level for 2 µs or more. Then the RESET pin is returned to an “H” level (the power source voltage should be between 3.0 V and 5.5 V, and between 4.0 V and 5.5 V for extended operating temperature version), reset is released. Internal operation does not begin until after 8 to 13 XIN clock cycles are completed.
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HARDWARE FUNCTIONAL DESCRIPTION XIN φ RESET RESETOUT (internal reset) SYNC Address ? ? ? ? ? FFFC FFFD ADH, ADL Reset address from the vector table ? Data XIN: 8 to 13 clock cycles ? ? ? ? ADL ADH Notes 1: f(XIN) and f(φ) are in the relationship: f(X IN)=2 • f(φ). 2: A question mark (?) indicates an undefined status that depends on the previous status. Fig.
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HARDWARE FUNCTIONAL DESCRIPTION Clock Generating Circuit When the STP status is released, prescaler 12 and timer 1 will start counting and reset will not be released until timer 1 underflows, so set the timer 1 interrupt enable bit to “0” before the STP instruction is executed. An oscillation circuit can be formed by connecting a resonator between XIN and X OUT. To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open.
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HARDWARE FUNCTIONAL DESCRIPTION Processor Modes Single-chip mode, memory expansion mode, and microprocessor mode can be selected by changing the contents of the processor mode bits CM 0 and CM 1 (bits 0 and 1 of address 003B 16). In memory expansion mode and microprocessor mode, memory can be expanded externally through ports P0 to P3. In these modes, ports P0 to P3 lose their I/O port functions and become bus pins. Table 8.
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HARDWARE FUNCTIONAL DESCRIPTION Bus control with memory expansion The 3800 group has a built-in ONW function to facilitate access to external memory and I/O devices in memory expansion mode or microprocessor mode. If an “L” level signal is input to the ONW pin when the CPU is in a read or write state, the corresponding read or write cycle is extended by one cycle of φ. During this extended period, the RD or WR signal remains at “L”.
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HARDWARE NOTES ON PROGRAMMING NOTES ON PROGRAMMING Processor Status Register Serial I/O The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations.
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HARDWARE DATA REQUIRED FOR MASK ORDERS/ROM PROGRAMMING METHOD DATA REQUIRED FOR MASK ORDERS ROM PROGRAMMING METHOD The following are necessary when ordering a mask ROM production: 1. Mask ROM Order Confirmation Form 2. Mark Specification Form 3. Data to be written to ROM, in EPROM form (three identical copies) The built-in PROM of the blank One Time PROM version and builtin EPROM version can be read or programmed with a generalpurpose PROM programmer using a special programming adapter.
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HARDWARE FUNCTIONAL DESCRIPTION SUPPLEMENT FUNCTIONAL DESCRIPTION SUPPLEMENT Interrupt 3800 group permits interrupts on the basis of 15 sources. It is vector interrupts with a fixed priority system. Accordingly, when two or more interrupt requests occur during the same sampling, the higher-priority interrupt is accepted first. This priority is determined by hardware, but variety of priority processing can be performed by software, using an interrupt enable bit and an interrupt disable flag.
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HARDWARE FUNCTIONAL DESCRIPTION SUPPLEMENT Timing After Interrupt The interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently in execution. Figure 32 shows a timing chart after an interrupt occurs, and Figure 33 shows the time up to execution of the interrupt processing routine.
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CHAPTER 2 APPLICATION 2.1 2.2 2.3 2.4 2.
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APPLICATION 2.1 I/O port 2.1 I/O port 2.1.
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APPLICATION 2.1 I/O port 2.1.
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APPLICATION 2.1 I/O port 2.1.3 Handling of unused pins Table 2.1.1 Handling of unused pins (in single-chip mode) Name of Pins/Ports P0, P1, P2, P3, P4, P5, P6, P7 X OUT Handling • Set to the input mode and connect to V CC or V SS through a resistor of 1 k to 10 k . • Set to the output mode and open at “L” or “H.” Open (only when using external clock). Table 2.1.
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APPLICATION 2.2 Timer 2.2 Timer 2.2.1 Memory map of timer 002016 Prescaler 12 (PRE12) 002116 Timer 1 (T1) 002216 Timer 2 (T2) 002316 Timer XY mode register (TM) 002416 Prescaler X (PREX) 002516 Timer X (TX) 002616 Prescaler Y (PREY) 002716 Timer Y (TY) 003C16 Interrupt request register 1 (IREQ1) 003D16 Interrupt request register 2 (IREQ2) 003E16 Interrupt control register 1 (ICON1) 003F16 Interrupt control register 2 (ICON2) Fig. 2.2.
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APPLICATION 2.2 Timer 2.2.2 Related registers Prescaler 12, Prescaler X, Prescaler Y b7 b6 b5 b4 b3 b2 b1 b0 Prescaler 12 (PRE12), Prescaler X (PREX), Prescaler Y (PREY) [Address : 2016, 2416, 2616] B 0 1 Function ● ● ● 2 The count value of each prescaler is set. The value set in this register is written to both the prescaler and the prescaler latch at the same time. When the prescaler is read out, the value (count value) of the prescaler is read out.
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APPLICATION 2.2 Timer Timer 2, Timer X, Timer Y b7 b6 b5 b4 b3 b2 b1 b0 Timer 2 (T2), Timer X (TX), Timer Y (TY) [Address : 2216, 2516, 2716] B 0 Function ● ● 1 2 ● The count value of each timer is set. The value set in this register is written to both the Timer and the Timer latch at the same time. When the Timer is read out, the value (count value) of the Timer is read out. At reset R W 1 1 1 3 1 4 1 5 1 6 1 7 1 Fig. 2.2.
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APPLICATION 2.2 Timer AA AA AA Timer XY mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer XY mode register (TM) [Address : 2316] Name B 0 Timer X operating mode bit Function b1 b0 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 1 : Pulse width measurement mode 2 CNTR0 active edge switch bit It depends on the operating mode of the Timer X (refer to Table 2.2.1).
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APPLICATION 2.
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APPLICATION 2.
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APPLICATION 2.2 Timer 2.2.3 Timer application examples (1) Basic functions and uses [Function 1] Control of Event interval (Timer X, Timer Y, Timer 1, Timer 2) The Timer count stop bit is set to “0” after setting a count value to a timer. Then a timer interrupt request occurs after a certain period.
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APPLICATION 2.2 Timer (2) Timer application example 1 : Clock function (measurement of 250 ms) Outline : The input clock is divided by a timer so that the clock counts up every 250 ms. Specifications : • The clock f(XIN) = 4.19 MHz (2 22 Hz) is divided by a timer. • The clock is counted at intervals of 250 ms by the Timer X interrupt. Figure 2.2.10 shows a connection of timers and a setting of division ratios, Figures 2.2.11 show a setting of related registers, and Figure 2.2.12 shows a control procedure.
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APPLICATION 2.2 Timer Timer XY mode register (Address : 2316) b7 b0 1 TM 0 0 Timer X operating mode bits : Timer mode Timer X count stop bit : Count stop Set to “0” at starting to count.
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APPLICATION 2.2 Timer Control procedure : Figure 2.2.12 shows a control procedure. ● RESET Initialization SEI X : This bit is not used in this application. Set it to “0” or “1.” It’s value can be disregarded. ● All interrupts : Disabled .... TM XXXX1X002 (Address : 2316) ICON1 (Address : 3E16), bit4 1 ● ● Timer X : Timer mode Timer X interrupt : Enabled .... PREX (Address : 2416) TX (Address : 2516) 256 – 1 256 – 1 ● Set “division ratio – 1” to the Prescaler X and Timer X. ....
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APPLICATION 2.2 Timer (3) Timer application example 2 : Piezoelectric buzzer output Outline : The rectangular waveform output function of a timer is applied for a piezoelectric buzzer output. Specifications : • The rectangular waveform resulting from dividing clock f(X IN ) = 4.19 MHz into about 2 kHz (2048 Hz) is output from the P5 4/CNTR 0 pin. • The level of the P5 4/CNTR0 pin fixes to “H” while a piezoelectric buzzer output is stopped. Figure 2.2.
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APPLICATION 2.2 Timer Timer XY mode register (Address : 2316) b7 b0 TM 1 0 0 1 Timer X operating mode bits : Pulse output mode CNTR 0 active edge switch bit : Output from the “H” level Timer X count stop bit : Count stop Set to “0” at starting to count. Timer X (Address : 2516) b7 TX b0 63 Set “division ratio – 1” Prescaler X (Address : 2416) b7 PREX b0 0 Fig. 2.2.15 Setting of related registers [Piezoelectric buzzer output] Control procedure : Figure 2.2.16 shows a control procedure.
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APPLICATION 2.2 Timer (4) Timer application example 3 : Measurement of frequency Outline : The following two values are compared for judging if the frequency is within a certain range. • A value counted a pulse which is input to P5 5/CNTR 1 pin by a timer. • A referance value Specifications : • The pulse is input to the P55 /CNTR 1 pin and counted by the Timer Y. • A count value is read out at the interval of about 2 ms (Timer 1 interrupt interval : 244 µs ✕ 8).
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APPLICATION 2.2 Timer Timer XY mode register (Address : 2316) b7 TM b0 1 1 1 0 Timer Y operating mode bit : Event counter mode CNTR1 active edge switch bits : Count at falling edge Timer Y count stop bit : Count stop Set to “0” at starting to count.
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APPLICATION 2.2 Timer Control procedure : Figure 2.2.19 shows a control procedure. ● X : This bit is not used in this application. RESET Set it to “0” or “1.” It’s value can be disregarded. Initialization SEI .... ● (Address : 23 16) 1110XXXX 2 TM PRE12 (Address : 20 16) 64–1 (Address : 21 16) T1 8–1 PREY (Address : 26 16) 1–1 (Address : 27 16) TY 256–1 ICON1 (Address : 3E 16), bit6 1 ● ● .... (Address : 23 16), bit7 0 ● ....
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APPLICATION 2.2 Timer (5) Timer application example 4 : Measurement of pulse width of FG pulse generated by motor Outline : The “H” level width of a pulse input to the P5 4/CNTR 0 pin is counted by Timer X. An underflow is detected by Timer X interrupt and an end of the input pulse “H” level is detected by CNTR0 interrupt. Specifications : • The “H” level width of a FG pulse input to the P54 /CNTR0 pin is counted by Timer X. (Example : When the clock frequency is 4.19 MHz, the count source would be 3.
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APPLICATION 2.2 Timer Timer XY mode register (Address : 2316) b7 b0 TM 1 0 1 1 Timer X operating mode bits : Pulse width measurement mode CNTR0 active edge switch bit : Count “H” level width Timer X count stop bit : Count stop Set to “0” at starting to count.
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APPLICATION 2.2 Timer Figure 2.2.22 shows a control procedure. RESET ● X : This bit is not used in this application. Set it to “0” or “1.” It’s value can be disregarded. Initialization SEI ● .... ● ● ● ● ....
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APPLICATION 2.3 Serial I/O 2.3 Serial I/O 2.3.
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APPLICATION 2.3 Serial I/O 2.3.2 Related registers Transmit/Receive buffer register b7 b6 b5 b4 b3 b2 b1 b0 Transmit/Receive buffer register (TB/RB) [Address : 1816] Function B At reset 0 A transmission data is written to or a receive data is read out ? 1 ? from this buffer register. • At writing : a data is written to the Transmit buffer register. • At reading : a content of the Receive buffer register is read out.
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APPLICATION 2.
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APPLICATION 2.3 Serial I/O Baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 Baud rate generator (BRG) [Address : 1C16] Function B A count value of Baud rate generator is set. 0 At reset R W ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? Fig. 2.3.
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APPLICATION 2.
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APPLICATION 2.3 Serial I/O 2.3.3 Serial I/O connection examples (1) Control of peripheral IC equipped with CS pin There are connection examples using a clock synchronous serial I/O mode. Figure 2.3.10 shows connection examples of a peripheral IC equipped with the CS pin. (1) Only transmission (using the RXD pin as an I/O port) Port CS SCLK CLK TXD DATA 3800 group Peripheral IC (OSD controller etc.
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APPLICATION 2.3 Serial I/O (2) Connection with microcomputer Figure 2.3.11 shows connection examples of the other microcomputers.
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APPLICATION 2.3 Serial I/O 2.3.4 Setting of serial I/O transfer data format A clock synchronous or clock asynchronous (UART) is selected as a data format of the serial I/O. Figure 2.3.12 shows a setting of serial I/O transfer data format.
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APPLICATION 2.3 Serial I/O 2.3.5 Serial I/O application examples (1) Communication using a clock synchronous serial I/O (transmit/receive) Outline : 2-byte data is transmitted and received through the clock synchronous serial I/O. The signal is used for communication control. S RDY Figure 2.3.13 shows a connection diagram, and Figure 2.3.14 shows a timing chart. Transmitting side Receiving side P42/INT0 SRDY SCLK1 SCLK TXD RXD 3800 group 3800 group Fig. 2.3.
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APPLICATION 2.3 Serial I/O Transmitting side Serial I/O status register (Address : 1916) b7 b0 SIOSTS Transmit buffer empty flag • Check to be transferred data from the Transmit buffer register to Transmit shift register. • Writable the next transmission data to the Transmit buffer register at being set to “1.
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APPLICATION 2.3 Serial I/O Receiving side Serial I/O status register (Address : 1916) b7 b0 SIOSTS Receive buffer full flag Check a completion of receiving 1-byte data with this flag.
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APPLICATION 2.3 Serial I/O Control procedure : Figure 2.3.17 shows a control procedure at a transmitting side, and Figure 2.3.18 shows a control procedure at a receiving side. ●X RESET : This bit is not used in this application. Set it to “0” or “1.” It’s value can be disregarded. Initialization .....
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APPLICATION 2.3 Serial I/O ● RESET X : This bit is not used in this application. Set it to “0” or “1.” It’s value can be disregarded. Initialization ..... SIOCON (Address : 1A16 ) 1111X11X2 N Pass 2 ms? ● An interval of 2 ms is generated by a timer. Y TB/RB (Address : 1816 ) Dummy data ● SRDY output SRDY signal is output by writing data to the TB/RB. Using the SRDY , the transmit enabled bit (bit4) of the SIOCON is set to “1.
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APPLICATION 2.3 Serial I/O (2) Output of serial data (control of a peripheral IC) Outline : 4-byte data is transmitted and received through the clock synchronous serial I/O. The CS signal is output to a peripheral IC through the port P53. P53 CS SCLK CLK CS CLK DATA TXD 3800 group DATA Peripheral IC Fig. 2.3.19 Connection diagram [Output of serial data] Specifications : • • • • • The Serial I/O is used.
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APPLICATION 2.3 Serial I/O Figure 2.3.21 shows a setting of serial I/O related registers, and Figure 2.3.22 shows a setting of serial I/O transmission data.
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APPLICATION 2.3 Serial I/O Control procedure : When the registers are set as shown in Figure 2.3.21, the Serial I/O can transmit 1-byte data simply by writing data to the Transmit buffer register. Thus, after setting the CS signal to “L,” write the transmission data to the Receive buffer register on a 1-byte base, and return the CS signal to “H” when the desired number of bytes have been transmitted. Figure 2.3.23 shows a control procedure of serial I/O.
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APPLICATION 2.3 Serial I/O (3) Cyclic transmission or reception of block data (data of a specified number of bytes) between microcomputers [without using an automatic transfer] Outline : When a clock synchronous serial I/O is used for communication, synchronization of the clock and the data between the transmitting and receiving sides may be lost because of noise included in the synchronizing clock. Thus, it is necessary to be corrected constantly.
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APPLICATION 2.3 Serial I/O The communication is performed according to the timing shown below. In the slave unit, when a synchronizing clock is not input within a certain time (heading adjustive time), the next clock input is processed as the beginning (heading) of a block. When a clock is input again after one block (8 byte) is received, the clock is ignored. Figure 2.3.26 shows a setting of related registers.
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APPLICATION 2.3 Serial I/O Control procedure : Control in the master unit After a setting of the related registers is completed as shown in Figure 2.3.33, in the master unit transmission or reception of 1-byte data is started simply by writing transmission data to the Transmit buffer register. To perform the communication in the timing shown in Figure 2.3.25, therefore, take the timing into account and write transmission data.
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APPLICATION 2.3 Serial I/O Control in the slave unit After a setting of the related registers is completed as shown in Figure 2.3.26, the slave unit becomes the state which is received a synchronizing clock at all times, and the Serial I/O receive interrupt request bit is set to “1” every time an 8-bit synchronous clock is received. By the serial I/O receive interrupt processing routine, the data to be transmitted next is written to the Transmit buffer register after received data is read out.
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APPLICATION 2.3 Serial I/O (4) Communication (transmit/receive) using an asynchronous serial I/O (UART) Point : 2-byte data is transmitted and received through an asynchronous serial I/O. The port P4 0 is used for communication control. Figure 2.3.29 shows a connection diagram, and Figure 2.3.30 shows a timing chart. Transmitting side Receiving side P40 P40 TXD R XD 3800 group 3800 group Fig. 2.3.
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APPLICATION 2.3 Serial I/O Table 2.3.1 shows setting examples of Baud rate generator (BRG) values and transfer bit rate values, Figure 2.3.31 shows a setting of related registers at a transmitting side, and Figure 2.3.32 shows a setting of related registers at a receiving side. Table 2.3.1 Setting examples of Baud rate generator values and transfer bit rate values Transfer bit BRG count at f(X IN) = 4.9152 MHZ at f(X IN) = 7.
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APPLICATION 2.3 Serial I/O Transmitting side Serial I/O status register (Address : 1916) b7 b0 SIOSTS Transmit buffer empty flag • Check to be transferred data from the Transmit buffer register to the Transmit shift register. • Writable the next transmission data to the Transmit buffer register at being set to “1.” Transmit shift register shift completion flag Check a completion of transmitting 1-byte data with this flag.
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APPLICATION 2.3 Serial I/O Receiving side Serial I/O status register (Address : 1916) b7 b0 SIOSTS Receive buffer full flag Check a completion of receiving 1-byte data with this flag. “1” : at completing to receive “0” : at reading out a content of the Receive buffer register Overrun error flag “1” : when data are ready to be transferred to the Receive shift register in the state of storing data into the Receive buffer register. Parity error flag “1” : when parity error occurs at enabled parity.
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APPLICATION 2.3 Serial I/O Control procedure : Figure 2.3.33 shows a control procedure at a transmitting side, and Figure 2.3.34 shows a control procedure at a receiving side. RESET ●X : This bit is not used in this application. Set it to “0” or “1.” It’s value can be disregarded. Initialization .... SIOCON UARTCON BRG P4 P4D (Address : 1A16) 1001X0012 (Address : 1B16) 000010002 (Address : 1C16) 8–1 (Address : 0816), bit0 0 XXXXXXX12 (Address : 0916) ● Set port P40 for a communication control.
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APPLICATION 2.3 Serial I/O ●X RESET : This bit is not used in this application. Set it to “0” or “1.” It’s value can be disregarded. Initialization .... SIOCON (Address : 1A 16) UARTCON (Address : 1B 16) (Address : 1C 16) BRG (Address : 09 16) P4D 1010X001 2 00001000 2 8 —1 XXXXXXX02 SIOSTS (Address : 1916 ), bit1? 0 ● 1 ● Read out a reception data from RB (Address : 1816) ● SIOSTS (Address : 1916 ), bit6? 1 Check a completion of receiving.
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APPLICATION 2.4 Processor mode 2.4 Processor mode 2.4.1 Memory map of processor mode 003B16 CPU mode register (CPUM) Fig. 2.4.1 Memory map of processor mode related register 2.4.2 Related register CPU mode register b7 b6 b5 b4 b3 b2 b1 b0 CPU mode register (CPUM) [Adress : 3B16 ] B Name 0 Processor mode bits 1 2 Stack page selection bit Function 00 : Single-chip mode 01 : Memory expansion mode 10 : Microprocessor mode 11 : Not available 0 : 0 page 1 : 1 page 3 Nothing is allocated for these bits.
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APPLICATION 2.4 Processor mode 2.4.3 Processor mode application examples (1) Application example of memory expansion in the case where the ONW (One-Wait) function is not used Outline : The external memory is accessed in the microprocessor mode. At f(X IN) = 8 MHz, an available RAM is given by the following : • OE access time : ta (OE) ≤ 50 ns • Setup time for writing data : tsu (D) ≤ 65 ns For example, the M5M5256BP-10 whose address access is 100 ns is available. Figure 2.4.
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APPLICATION 2.4 Processor mode Figure 2.4.4, Figure 2.4.5 and Figure 2.4.6 show a standard timing at 8 MHz (No-Wait).
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APPLICATION 2.4 Processor mode A0–A7 Address (low-order) (Port P0) A8–A14 Address (high-order) (Port P1) S (A15) tWL(WR) 125 ns - 10 ns (min) td(AH—WR) W (WR of 3800) 125 ns - 35 ns (min) td(WR—DB) 65 ns (max) DQ1–DQ8 Data (Port P2) tsu(D) 35 ns (min) OE (RD of 3800) “ H ” level td(AH—WR) tWL(WR) td(WR—DB) tsu(D) : : : : WR delay time after outputting address of 3800 WR pulse width of 3800 Data bus delay time after WR of 3800 Data setup time of M5M5256BP Fig. 2.4.
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APPLICATION 2.4 Processor mode (2) Application example of memory expansion in the case where the ONW (One-Wait) function is used Outline : ONW function is used when the external memory access is slow. If “L” level signal is input to the P32 /ONW pin while the CPU is in the read or write status, the read or write cycle corresponding to 1 cycle of φ is extended. In the extended period, the RD or WR signal is kept at the “L” level.
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APPLICATION 2.5 Reset 2.5 Reset 2.5.1 Connection example of reset IC 91 1 VCC Power source M62022L 5 Output 35 RESET Delay capacity 4 GND 0.1 µF 40 3 VSS 3800 group Fig. 2.5.1 Example of Poweron reset circuit Figure 2.5.2 shows the system example which switch to the RAM backup mode by detecting a drop of the system power source voltage with the INT interrupt.
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CHAPTER 3 APPENDIX 3.1 Electrical characteristics 3.2 Standard characteristics 3.3 Notes on use 3.4 Countermeasures against noise 3.5 List of registers 3.6 Mask ROM ordering method 3.7 Mark specification form 3.8 Package outline 3.9 List of instruction codes 3.10 Machine instructions 3.11 SFR memory map 3.
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APPENDIX 3.1 Electrical characteristics 3.1 Electrical characteristics 3.1.1 Absolute maximum ratings Table 3.1.
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APPENDIX 3.1 Electrical characteristics 3.1.3 Electrical characteristics Table 3.1.3 Electrical characteristics (VCC = 3.0 to 5.
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APPENDIX 3.1 Electrical characteristics 3.1.4 Timing requirements and Switching characteristics Table 3.1.4 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol t W(RESET) t c(X IN) t WH(X IN) t WL(X IN) t c(CNTR) t WH(CNTR) t WL(CNTR) t WH(INT) t WL(INT) t c(S CLK) t WH(S CLK) t WL(S CLK) tsu(R X D–SCLK ) th(S CLK–RX D) Parameter Min.
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APPENDIX 3.1 Electrical characteristics Table 3.1.6 Switching characteristics (1) (VCC = 4.0 to 5.
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APPENDIX 3.1 Electrical characteristics Table 3.1.8 Timing requirements in memory expansion mode and microprocessor mode (1) (V CC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol t su(ONW–φ) t h(φ–ONW) t su(DB–φ) t h(φ–DB) t su(ONW–RD) t su(ONW–WR) t h(RD–ONW) t h(WR–ONW) t su(DB–RD) t h(RD–DB) Table 3.1.
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APPENDIX 3.1 Electrical characteristics Table 3.1.10 Timing requirements in memory expansion mode and microprocessor mode (2) (VCC = 3.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol t su(ONW–φ) t h(φ–ONW) t su(DB–φ) t h(φ–DB) t su(ONW–RD) t su(ONW–WR) th (RD–ONW) t h(WR–ONW) t su(DB–RD) t h(RD–DB) Limits Parameter Min.
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APPENDIX 3.1 Electrical characteristics 3.1.5 Absolute maximum ratings (Extended operating temperature version) Table 3.1.
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APPENDIX 3.1 Electrical characteristics 3.1.7 Electrical characteristics (Extended operating temperature version) Table 3.1.14 Electrical characteristics (Extended operating temperature version) (V CC = 4.0 to 5.
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APPENDIX 3.1 Electrical characteristics 3.1.8 Timing requirements and Switching characteristics (Extended operating temperature version) Table 3.1.15 Timing requirements (Extended operating temperature version) (V CC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Symbol t W(RESET) t c(X IN) t WH(X IN) t WL(X IN) t c(CNTR) t WH(CNTR) t WL(CNTR) t WH(INT) t WL(INT) t c(S CLK) t WH(S CLK) t WL(S CLK) tsu(R X D–SCLK ) th(S CLK–RX D) Parameter Min.
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APPENDIX 3.1 Electrical characteristics Table 3.1.17 Timing requirements in memory expansion mode and microprocessor mode (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Symbol t su(ONW–φ) t h(φ–ONW) t su(DB–φ) t h(φ–DB) t su(ONW–RD) t su(ONW–WR) t h(RD–ONW) t h(WR–ONW) t su(DB–RD) t h(RD–DB) Limits Parameter Min.
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APPENDIX 3.1 Electrical characteristics 3.1.9 Timing diagram Timing Diagram tC(CNTR) tWL(CNTR) tWH(CNTR) 0.8 VCC CNTR0, CNTR1 0.2 VCC tWL(INT) tWH(INT) 0.8 VCC INT0–INT5 0.2 VCC tW(RESET) RESET 0.8 VCC 0.2 VCC tC(XIN) tWL(XIN) tWH(XIN) 0.8 VCC XIN 0.2 VCC tC(SCLK) tWL(SCLK) tf SCLK tWH(S CLK) tr 0.8 VCC 0.2 VCC tsu(SCLK-RXD) th(SCLK-RXD) 0.8 VCC 0.2 VCC RXD td(SCLK-TXD) TX D Fig. 3.1.
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APPENDIX 3.1 Electrical characteristics Timing Diagram in Memory Expansion Mode and Microprocessor Mode (1) tC(φ) tWL(φ) tWH(φ) φ 0.5 VCC tv(φ-AH) td(φ-AH) AD15–AD8 0.5 VCC td(φ-AL) AD7–AD0 tv(φ-AL) 0.5 VCC tv(φ-SYNC) td(φ-SYNC) SYNC 0.5 VCC td(φ-WR) RD,WR tv(φ-WR) 0.5 VCC th(φ-ONW) tSU(ONW-φ) 0.8 VCC 0.2 VCC ONW tSU(DB-φ) th(φ-DB) 0.8 VCC 0.2 VCC DB0–DB7 (At CPU reading) td(φ-DB) DB0–DB7 (At CPU writing) tv(φ-DB) 0.5 VCC Timing Diagram in Microprocessor Mode RESET 0.
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APPENDIX 3.1 Electrical characteristics Timing Diagram in Memory Expansion Mode and Microprocessor Mode (2) tWL(RD) tWL(WR) RD,WR 0.5 VCC td(AH-RD) td(AH-WR) AD15–AD8 tv(RD-AH) tv(WR-AH) 0.5 VCC td(AL-RD) td(AL-WR) AD7–AD0 tv(RD-AL) tv(WR-AL) 0.5 VCC th(RD-ONW) th(WR-ONW) tsu(ONW-RD) tsu(ONW-WR) ONW 0.8 VCC 0.2 VCC (At CPU reading) tWL(RD) RD 0.5 VCC tSU(DB-RD) 0.8 VCC 0.2 VCC DB0–DB7 (At CPU writing) tWL(WR) WR 0.5 VCC tv(WR-DB) td(WR-DB) DB0–DB7 0.5 VCC Fig. 3.1.
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APPENDIX 3.2 Standard characteristics 3.2 Standard characteristics 3.2.1 Power source current characteristic examples Figures 3.2.1 and Figure 3.2.2 show power source current characteristic examples. [Measuring condition : 25 °C] Rectangular waveform Power source current (mA) 8 Vcc = 5.5 V, Ta = 25 7 6 5 Vcc = 4.0 V, Ta = 25 4 3 2 Vcc = 3.0 V, Ta = 25 1 0 0 1 2 3 4 5 6 7 8 Frequency f(XIN) (MHz) Fig. 3.2.
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APPENDIX 3.2 Standard characteristics 3.2.2 Port standard characteristic examples Figures 3.2.3, Figure 3.2.4, Figure 3.2.5 and Figure 3.2.6 show port standard characteristic examples. [Port P00 IOH–V OH characteristic (P-channel drive)] (Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6, P7) IOH (mA) – 50 – 45 Vcc = 5.0 V, Ta = 90 – 40 – 35 – 30 Vcc = 4.0 V, Ta = 90 – 25 – 20 Vcc = 3.0 V, Ta = 90 – 15 – 10 – 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VOH (V) Fig. 3.2.
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APPENDIX 3.2 Standard characteristics [Port P00 IOL –VOL characteristic (N-channel drive)] (Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6, P7) IOL (mA) 50 Vcc = 5.0 V, Ta = 90 45 40 35 Vcc = 4.0 V, Ta = 90 30 25 Vcc = 3.0 V, Ta = 90 20 15 10 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOL (V) Fig. 3.2.
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APPENDIX 3.3 Notes on use 3.3 Notes on use 3.3.1 Notes on interrupts (1) Sequence for switching an external interrupt detection edge When the external interrupt detection edge must be switched, make sure the following sequence. Reason The interrupt circuit recognizes the switching of the detection edge as the change of external input signals. This may cause an unnecessary interrupt.
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APPENDIX 3.
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APPENDIX 3.3 Notes on use 3.3.4 Notes on input and output pins (1) Fix of a port input level in stand-by state Fix input levels of an input and an I/O port for getting effect of low-power dissipation in stand-by state*, especially for the I/O ports of the N-channel open-drain. Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor.
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APPENDIX 3.3 Notes on use 3.3.5 Notes on memory expansion mode and microprocessor mode (1) Writing data to the port latch of port P3 In the memory expansion or the microprocessor mode, ports P3 0 and P31 can be used as the output port. Use the LDM or STA instruction for writing data to the port latch (address 000616) of port P3. When using a read-modify-write instruction (the SEB or the CLB instruction), allocate the read and the write enabled memory at address 000616.
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APPENDIX 3.3 Notes on use 3.3.6 Notes on built-in PROM (1) Programming adapter To write or read data into/from the internal PROM, use the dedicated programming adapter and general-purpose PROM programmer as shown in Table 3.3.1. Table 3.3.
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APPENDIX 3.3 Notes on use Table 3.3.
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APPENDIX 3.4 Countermeasures against noise 3.4 Countermeasures against noise Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 3.4.1 Shortest wiring length The wiring on a printed circuit board can be as an antenna which feeds noise into the microcomputer.
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APPENDIX 3.4 Countermeasures against noise AAA AAA AA AA AA AA AAA AA AAAA AAA An example of VSS patterns on the underside of a printed circuit board Noise Oscillator wiring pattern example XIN XOUT VSS N.G. XIN XOUT VSS XIN XOUT VSS O.K. Separate the VSS line for oscillation from other VSS lines Fig. 3.4.
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APPENDIX 3.4 Countermeasures against noise 3.4.3. Consideration for oscillator Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. Microcomputer Mutual inductance M (1) Keeping an oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows.
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APPENDIX 3.4 Countermeasures against noise 3.4.5 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software.
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APPENDIX 3.5 List of registers 3.
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APPENDIX 3.5 List of registers Transmit/Receive buffer register b7 b6 b5 b4 b3 b2 b1 b0 Transmit/Receive buffer register (TB/RB) [Address : 1816] Function B At reset 0 A transmission data is written to or a receive data is read out ? 1 ? from this buffer register. • At writing : a data is written to the Transmit buffer register. • At reading : a content of the Receive buffer register is read out.
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APPENDIX 3.
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APPENDIX 3.5 List of registers Baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 Baud rate generator (BRG) [Address : 1C16] Function B 0 A count value of Baud rate generator is set. At reset R W ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? Fig. 3.5.7 Structure of Baud rate generator Prescaler 12, Prescaler X, Prescaler Y b7 b6 b5 b4 b3 b2 b1 b0 Prescaler 12 (PRE12), Prescaler X (PREX), Prescaler Y (PREY) [Address : 2016, 2416, 2616] B 0 1 2 Function ● ● ● The count value of each prescaler is set.
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APPENDIX 3.5 List of registers Timer 1 b7 b6 b5 b4 b3 b2 b1 b0 Timer 1 (T1) [Address : 2116] B 0 ● ● 1 ● 2 Function At reset The count value of the Timer 1 is set. The value set in this register is written to both the Timer 1 and the Timer 1 latch at the same time. When the Timer 1 is read out, the value (count value) of the Timer 1 is read out. 1 R W 0 0 3 0 4 0 5 0 6 0 7 0 Fig. 3.5.
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APPENDIX 3.5 List of registers AA AA AA Timer XY mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer XY mode register (TM) [Address : 2316] Name B 0 Timer X operating mode bit Function b1 b0 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 1 : Pulse width measurement mode 2 CNTR0 active edge switch bit It depends on the operating mode of the Timer X (refer to Table 3.5.1).
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APPENDIX 3.
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APPENDIX 3.
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APPENDIX 3.
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APPENDIX 3.6 Mask ROM ordering method 3.6 Mask ROM ordering method GZZ-SH04-34B<13B0> Mask ROM number Date: Section head Supervisor signature signature Receipt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38002M2-XXXSP/FP MITSUBISHI ELECTRIC ❈ Customer TEL ( Company name Date issued Date: ) Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted.
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APPENDIX 3.6 Mask ROM ordering method GZZ-SH04-34B<13B0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38002M2-XXXSP/FP MITSUBISHI ELECTRIC We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type 27256 27512 The pseudo-command *=a$8000 .BYTEa ‘M38002M2–’ *=a$0000 .
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APPENDIX 3.6 Mask ROM ordering method GZZ-SH04-79B<16A0> Mask ROM number Receipt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38002M2DXXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature ❈ Customer TEL ( Company name Date issued Date: ) Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted.
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APPENDIX 3.6 Mask ROM ordering method GZZ-SH04-79B<16A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38002M2DXXXSP/FP MITSUBISHI ELECTRIC We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type 27256 27512 The pseudo-command *=a$8000 .BYTEa ‘M38002M2D’ *=a$0000 .
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APPENDIX 3.6 Mask ROM ordering method GZZ-SH03-22B<9YB0> Mask ROM number Date: Section head Supervisor signature signature Receipt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38002M4-XXXSP/FP MITSUBISHI ELECTRIC ❈ Customer TEL ( Company name Date issued Date: ) Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted.
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APPENDIX 3.6 Mask ROM ordering method GZZ-SH03-22B<9YB0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38002M4-XXXSP/FP MITSUBISHI ELECTRIC We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type 27256 27512 The pseudo-command *=a$8000 .BYTEa ‘M38002M4–’ *=a$0000 .
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APPENDIX 3.6 Mask ROM ordering method GZZ-SH05-12B<21A0> Mask ROM number Receipt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38002M4DXXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature ❈ Customer TEL ( Company name Date issued Date: ) Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted.
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APPENDIX 3.6 Mask ROM ordering method GZZ-SH05-12B<21A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38002M4DXXXSP/FP MITSUBISHI ELECTRIC We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type 27256 27512 The pseudo-command *=a$8000 .BYTEa ‘M38002M4D’ *=a$0000 .
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APPENDIX 3.6 Mask ROM ordering method GZZ-SH04-62B<14B0> 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38003M6-XXXSP/FP/HP MITSUBISHI ELECTRIC Receipt Mask ROM number Date: Section head Supervisor signature signature ❈ Customer TEL ( Company name Date issued Date: ) Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted.
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APPENDIX 3.6 Mask ROM ordering method GZZ-SH04-62B<14B0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38003M6-XXXSP/FP/HP MITSUBISHI ELECTRIC We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type 27256 27512 The pseudo-command *=a$8000 .BYTEa ‘M38003M6–’ *=a$0000 .
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APPENDIX 3.6 Mask ROM ordering method GZZ-SH04-30B<13B0> Mask ROM number Date: Section head Supervisor signature signature Receipt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38004M8-XXXSP/FP MITSUBISHI ELECTRIC ❈ Customer TEL ( Company name Date issued Date: ) Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted.
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APPENDIX 3.6 Mask ROM ordering method GZZ-SH04-30B<13B0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38004M8-XXXSP/FP MITSUBISHI ELECTRIC assembier source program. We recommend the use of the following pseudo-command to set the start address of the assembler EPROM type 27512 The pseudo-command *=a$0000 .BYTEa ‘M38004M8–’ Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed.
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APPENDIX 3.6 Mask ROM ordering method GZZ-SH07-23B<33A0> Mask ROM number Receipt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38004M8DXXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature ❈ Customer TEL ( Company name Date issued Date: ) Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted.
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APPENDIX 3.6 Mask ROM ordering method GZZ-SH07-23B<33A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38004M8DXXXSP/FP MITSUBISHI ELECTRIC assembier source program. We recommend the use of the following pseudo-command to set the start address of the assembler EPROM type 27512 The pseudo-command *=a$0000 .BYTEa ‘M38004M8D’ Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed.
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APPENDIX 3.7 Mark specification form 3.
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APPENDIX 3.
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APPENDIX 3.8 Package outline 3.8 Package outline 2.5/1 2.
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APPENDIX 3.8 Package outline 2.5/1 1.
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APPENDIX 3.8 Package outline 1.
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APPENDIX 3.9 Machine instructions 3.9 Machine instructions Addressing mode Symbol Function Details IMP OP n ADC (Note 1) (Note 5) When T = 0 A←A+M+C When T = 1 M(X) ← M(X) + M + C AND (Note 1) When TV= 0 A←A M When T = 1 V M(X) ← M(X) M ASL C← 7 0 ←0 IMM # OP n A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n Adds the carry, accumulator and memory contents. The results are entered into the accumulator.
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APPENDIX 3.
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APPENDIX 3.9 Machine instructions Addressing mode Symbol Function Details IMP OP n IMM # OP n BVC (Note 4) V = 0? Branches when the contents of overflow flag is “0”. BVS (Note 4) V = 1? Branches when the contents of overflow flag is “1”. CLB Ab or Mb ← 0 Clears the contents of the bit specified in the accumulator or memory to “0”. CLC C←0 Clears the contents of the carry flag to “0”. 18 2 1 CLD D←0 Clears the contents of decimal mode flag to D8 2 “0”.
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APPENDIX 3.
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APPENDIX 3.9 Machine instructions Addressing mode Symbol Function Details IMP OP n IMM # OP n JMP If addressing mode is ABS PCL ← ADL PCH ← ADH If addressing mode is IND PCL ← M (AD H, ADL) PCH ← M (ADH, AD L + 1) If addressing mode is ZP, IND PCL ← M(00, AD L) PCH ← M(00, AD L + 1) Jumps to the specified address.
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APPENDIX 3.
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APPENDIX 3.9 Machine instructions Addressing mode Symbol Function Details IMP IMM OP n # OP n A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n PHA M(S) ← A S←S–1 Saves the contents of the accumulator in memory at the address indicated by the stack pointer and decrements the contents of stack pointer by 1.
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APPENDIX 3.
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APPENDIX 3.9 Machine instructions Addressing mode Symbol Function Details IMP OP n STA M←A # OP n Stores the contents of accumulator in memory. Stops the oscillator. STP IMM 42 2 A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n 85 4 2 1 STX M←X Stores the contents of index register X in memory. 86 4 2 STY M←Y Stores the contents of index register Y in memory. 84 4 2 TAX X←A Transfers the contents of the accumulator to AA 2 index register X.
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APPENDIX 3.
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APPENDIX 3.10 List of instruction codes 3.
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APPENDIX 3.11 SFR memory map 3.
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APPENDIX 3.12 Pin configuration 3.
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APPENDIX 3.
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3800 Group User’s Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan H-EE418-A KI-9603