User manual

V850E2/MN4 A/D Converter Control
R01AN0923EJ0100 Rev.1.00 Page 3 of 26
Feb 13, 2012
1.1 Initialization
The general registers and functional pins are initialized.
<Port setup>
• Port n function control expansion registers (PFCEn)
• Port n function control registers (PFCn)
• Port n mode control registers (PMCn)
• Port n mode registers (PMn)
1.2 Basic Operation of the A/D Converter
This section describes the basic procedure of A/D conversion.
1. To optimize the start-up time between power being turned on and the start of conversion, adjust the stabilization
time setting in the ADC stabilization counter register (ADCAnCNT).
2. To enable the A/D converter (set ADCAnCTL0.ADCAnCE to 1 ), switch the power on and set up the resolution, the
ADCAn clock, the trigger mode, the conversion mode, the interrupt generation, the channel group, and other
settings in the following registers.
- ADCAnCTL1 register
- ADCAnCGi registers
- ADCAnIOCi registers
- ADCAnTSELi registers
3. To check that a result of A/D conversion is within a certain value range, enable the conversion result limit
comparison function for the desired channels (ADCAnCTL2.ADCAnRCKm) with upper and lower limits, and
specify the lower limit in the ADCAnLL register and the upper limit in the ADCAnUL register.
4. To discharge the capacitor in the common sample-and-hold circuit before the conversion, set
ADCAnCTL1.ADCAnDISC to 1 to enable the discharge function.
5. To enable or disable the buffer amplifier, set ADCAnCTL1.ADCAnBPC.
6. To enable the ADC, set ADCAnCTL0.ADCAnCE to 1. After the stabilization time has elapsed after power is turned
on or after the standby mode is exited, the A/D converter is ready for A/D conversion.
7. Depending on the specified trigger mode, A/D conversion is started by a given channel group (CG).
- Software trigger (setting ADCAnTRGi.ADCAnSTTi to 1)
- Hardware trigger (input signals ADCAnTTRGi)
If the A/D conversion of multiple CGs is triggered, the order of A/D conversion depends on the priority of the CGs.
8. When the A/D conversion on the channel specified by the ADCAnIOCi register end, the A/D conversion end
interrupt (INTADCAnTi) for the given channel is generated.
9. Read the results from the A/D conversion result registers, ADCAnLCR, ADCAnDBiCR, and ADCAnCmCR.
10. Monitor the following registers.
- ADCAnSTR1: To check whether the result of A/D conversion has been overwritten before being read according to
the field of application.
- ADCAnSTR0: To check whether the result of A/D conversion is within a specified range (only if the conversion
result limit comparison function is enabled).
11. To set the A/D converter again, disable the A/D converter by setting ADCAnCTL0.ADCAnCE to 0.