Specifications

V850E2/MN4 UARTJ Control
R01AN0926EJ0100 Rev.1.00 Page 9 of 30
Feb 07, 2012
4.1.3 Transmit Interrupt Processing
If the fill stage of the transmit FIFO matches the value set in the URTJnSLTP and write access to the URTJ1FTX
register is not executed, a transmit interrupt occurs.
During transmit interrupt processing, a flag (regarded as a transmit end flag) in the internal RAM is set to 1, indicating
that all data (16 bytes) have been transferred to the transmit FIFO.
Transmit interrupt
INTUAJ1TIC
Set transmission end flag to 1
End of processing
INTUAJ1TIC interrupt processing
Figure 4.3 Transmit Interrupt Processing