Specifications

V850E2/MN4 UARTJ Control
R01AN0926EJ0100 Rev.1.00 Page 4 of 30
Feb 07, 2012
1.1 Initialization
The general registers and functional pins are initialized.
<Port setup>
• Port n function control expansion registers (PFCEn)
• Port n function control registers (PFCn)
• Port n mode control registers (PMCn)
• Port n mode registers (PMn)
1.2 UARTJ Setup
The registers listed below are set up to control the operation of the UARTJ. See section 4.2 for details.
<UART control setup>
• UARTJn control register 0 (URTJnCTL0)
• UARTJn control register 1 (URTJnCTL1)
• UARTJn control register 2 (URTJnCTL2)
<FIFO control setup>
• UARTJn macro FIFO control register 0 (URTJnFCTL0)
• UARTJn macro FIFO control register 1 (URTJnFCTL1)
1.3 Interrupt Enabling
• Interrupts are enabled by the EI instruction.
1.4 Main Loop Processing
The main loop processing is mainly divided into two. It repeatedly controls transmission/reception and awaits the end of
transmission/reception. If transmit data is written to the URTJnFTX register after the operation of the UARTJ is set, the
data is written to the transmit FIFO. The data stored in the transmit FIFO is transferred to the transmit shift register,
after which serial transmission starts via the TXDnF pin.
In this sample program, the transmitting UARTJ1 transmits 16-byte data and the receiving UARTJ3 receives the 16-
byte data from the UARJ1. The internal RAM has the 16-byte (one byte (one block data)  16) user transmit array to
store transmit data and the 16-byte user receive array to store receive data.
When a transmit/receive interrupt or a status interrupt occurs during the main loop processing, the corresponding
interrupt processing is executed. In this sample program, interrupts occur at the timings listed below. See section 4 for
the details of the individual interrupt processing.
• Transmit interrupt: When the transmit FIFO becomes empty
• Receive interrupt: When the receive FIFO becomes full
• Status interrupt: When an error occurs during reception or transmission