Specifications

V850E2/MN4 UARTJ Control
R01AN0926EJ0100 Rev.1.00 Page 23 of 30
Feb 07, 2012
4.2.8 FIFO Status Clear Register (URTJnFSTC)
The error flags in URTJnFSTR1 are set when a timeout error, an overflow error, and an overrun error occur. The
URTJnFSTC register can be used to clear the error flags in URTJnFSTR1. The transmit/receive FIFO pointers can also
be cleared.
In this sample program, the corresponding error flags are cleared by using the URTJnSTC and URTJnFSTC registers
when INTUAJnTIS is detected.
Figure 4.15 URTJnFSTC Register Format
Setting example:
URTJnFSTC = 0xe3; /* Clear receive error flags */
/* Clear timeout error flag */
/* Clear transmit FIFO overflow error flag */
/* Clear receive FIFO overrun error flag */
/* Clear transmit FIFO pointer */
/* Clear receive FIFO pointer */