Specifications

V850E2/MN4 UARTJ Control
R01AN0926EJ0100 Rev.1.00 Page 20 of 30
Feb 07, 2012
4.2.5 FIFO Control Register 0 (URTJnFCTL0)
The URTJnFCTL0 register defines the fill stages of the Rx FIFO and the Tx FIFO, at which the receive (INTUAJnTIR)
and transmit (INTUAJnTIT) interrupts requests are generated.
A receive interrupt request is generated when the fill stage of the receive FIFO reaches the value specified in
URTJnFCTL0.URTJnSLRP[3:0]. A transmit interrupt request is generated when the fill stage of the transmit FIFO
reaches the value specified in URTJnFCTL0.URTJnSLTP[3:0].
The fill stages of the receive FIFO and the transmit FIFO need to be specified according to the baud rate. In this sample
program, they are set to 16 bytes.
Figure 4.12 URTJnFCTL0 Register Format
Setting example:
URTJnFCTL0 = 0x0000; /* Receive FIFO interrupt level: 16 bytes */
/* Transmit FIFO interrupt level: 16 bytes */