Specifications

V850E2/MN4 UARTJ Control
R01AN0926EJ0100 Rev.1.00 Page 19 of 30
Feb 07, 2012
Figure 4.11 URTJnCTL1 Register Format (3/3)
Setting example:
URTJnCTL1 = 0x5103; /* Disable BF reception during data reception */
/* Receive/transmit data bit length: 8 bits */
/* No parity */
/* Transmit data output: No inversion, receive data input: No inversion */
/* Transmit data stop bit count: 1 bit */
/* Transfer direction select: LSB first transfer */
/* Transmit interrupt request generated at the end of transmission */