Specifications

V850E2/MN4 UARTJ Control
R01AN0926EJ0100 Rev.1.00 Page 14 of 30
Feb 07, 2012
Setting example
URTJnCTL2 = 0x60D9; /* Assume that PCLK is set to 66.667 MHz */
/* PRSCLK (1/8), baud rate clock (2*217) */
/* 19200≈PCLK/ (8*2*217) */