Specifications

V850E2/MN4 UARTJ Control
R01AN0926EJ0100 Rev.1.00 Page 11 of 30
Feb 07, 2012
4.1.5 Status Interrupt Processing
A status interrupt request occurs when an error occurs during transmission/reception.
• Data consistency error
• Timeout error
• Framing error
• Parity error
• Overrun error
• Overflow error
When an error is detected during transmission/reception, the correspondent error flags in the URTJnSTR1 and
URTJnFSTR1 registers are set to 1. Then, the UARTJ status interrupt processing clears the transmit/receive FIFO. The
transmit FIFO is cleared by waiting for a period equivalent to the one required to transfer 16 bytes of data. The receive
FIFO is cleared by reading all of the received data from it. The transmit flag and the receive flag in the internal RAM
are set to 1. The SFR error flags are cleared via the URTJnSTC and URTJnFSTC registers and the transmit/receive
interrupt request or the status interrupt request is also cleared. The UARTJ1 and UARTJ3 are temporarily stopped and
return to the main loop (Transmission/reception is resumed in the main loop processing).
The status interrupt processing below is common to the UARTJ1 and the UARTJ3.
Status interrupt
INTUAJ
TIS
INTUAJnTIS
NO
YES
Disable UARTJ transmission or reception
FIFO error?
Clear error flag and transmit/receive/status interrupt request
Await end of ransmission, read all data from recive
FIFO, and set transmission end flag and reception end flag
(in internal RAM) to 1
flag_uart_error = 1
flag_fifo_error = 1
UART ?
NO
YES
Figure 4.5 Status Interrupt Processing