APPLICATION NOTE V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Feb 07, 2012 Introduction This application note explains how to set up the UARTJ serial interface (with FIFO) and also gives an outline of the operation and describes the procedures for using a sample program. The sample program sets the baud rate to 19200 bps and executes serial communication between the UARTJ1 and the UARTJ3. The UARTJ1 transmits data and the UARTJ3 receives the data.
V850E2/MN4 1. UARTJ Control Overview This application note illustrates the usage examples of the UARTJ. The sample program makes the basic initial settings of the V850E2/MN4 microcontrollers, such as the selection of the clock frequency and the setup of port I/O. The main processing after the end of initialization executes serial communication between the UARTJ1 and the UARTJ3. The UARTJ1 transmits data and the UARTJ3 receives the data. The main points in the software are shown below. See sections 4.1.
V850E2/MN4 UARTJ Control The basic communication specifications are shown below. Receive I/F Transmit I/F Operation mode Transfer direction Parity bits during transmission/reception Transmit data of 1 frame Stop bit Baud rate Transmit/receive FIFO size R01AN0926EJ0100 Rev.1.
V850E2/MN4 1.1 UARTJ Control Initialization The general registers and functional pins are initialized. • • • • Port n function control expansion registers (PFCEn) Port n function control registers (PFCn) Port n mode control registers (PMCn) Port n mode registers (PMn) 1.2 UARTJ Setup The registers listed below are set up to control the operation of the UARTJ. See section 4.2 for details.
V850E2/MN4 2. UARTJ Control Usage Environment This section provides the circuit diagram and operating environment of the hardware on which this sample program is to run. 2.1 Circuit Diagram See “V850E2/MN4 Target Board User Manual: QB-V850E2MN4DUAL-TB (R20UT0683XJ)” for the details of the circuit diagram. This sample program performs serial communication between the UARTJ1 and the UARTJ3. The UARTJ1 transmits data and the UARTJ3 receives the data.
V850E2/MN4 3. UARTJ Control Software This section describes the file organization of the sample program. 3.1 File Organization The file organization of the sample program is summarized below. File Name (Tool Structure) crtE.s V850E2MN4.dir uartj.h main.c initial.c uartj_transmit.c uartj_receive.c interrupt.
V850E2/MN4 4. UARTJ Control Sample Application This section explains how to set up the UARTJ functions. 4.1 Flow Charts The flow charts of this sample program are given below. 4.1.1 Main Processing The main processing disables maskable interrupts first. After each setup ends, the maskable interrupts and transmit/receive status interrupts are enabled. The main loop processing repeatedly controls transmission/reception and awaits the end of FIFO transmission/reception.
V850E2/MN4 4.1.2 UARTJ Control Receive Interrupt Processing When data is received via the UARTJ, the data in the receive FIFO is read. If the stage of the receive FIFO matches the value set in the URTJnSLRP, a receive interrupt occurs. During receive interrupt processing, data is read from the receive FIFO and the receive data is stored in the user receive array the number of times the data has been received.
V850E2/MN4 4.1.3 UARTJ Control Transmit Interrupt Processing If the fill stage of the transmit FIFO matches the value set in the URTJnSLTP and write access to the URTJ1FTX register is not executed, a transmit interrupt occurs. During transmit interrupt processing, a flag (regarded as a transmit end flag) in the internal RAM is set to 1, indicating that all data (16 bytes) have been transferred to the transmit FIFO.
V850E2/MN4 4.1.4 UARTJ Control Transmit/Receive Control Processing When transmit data is written to the URTJ1FTX register after the initialization of the UARTJ, transmission starts. Receiving a start bit from the transmitter, the receiver starts reception. Transmission control transmit start Write transmit data from user transumit array to URTJ3FTX No Have all transmit data been transferred? YES End of processing transmit start continiuous transmission processing Figure 4.
V850E2/MN4 4.1.5 UARTJ Control Status Interrupt Processing A status interrupt request occurs when an error occurs during transmission/reception. • • • • • • Data consistency error Timeout error Framing error Parity error Overrun error Overflow error When an error is detected during transmission/reception, the correspondent error flags in the URTJnSTR1 and URTJnFSTR1 registers are set to 1. Then, the UARTJ status interrupt processing clears the transmit/receive FIFO.
V850E2/MN4 4.2 UARTJ Control Register Setup This section explains how to set up the relevant registers according to the flow charts shown in section 4.1. The registers described below must be configured to control the UARTJ. 4.2.1 Port Setup The program described in this application note executes serial transmission/reception by using two macros, the UARTJ1 and the UARTJ3. The relevant ports must be set up so that the pins for the UARTJ1 and the UARTJ3 are enabled. The LEDs are connected to port 13.
V850E2/MN4 4.2.2 UARTJ Control UARTJn Control Register 2 (URTJnCTL2) The UARTJnCTL2 register defines the baud rates of the serial data transfers in which the UARTJn macros are used. The transmit/receive clocks are generated from PCLK. The frequency of the clock signal from PCLK is divided by a prescaler and the clock of the specified baudrate is generated by the baudrate generator. In this sample program, the baudrate is set to 19,200 bps. Figure 4.6 URTJnCTL2 Register Format R01AN0926EJ0100 Rev.1.
V850E2/MN4 UARTJ Control Setting example URTJnCTL2 = 0x60D9; R01AN0926EJ0100 Rev.1.00 Feb 07, 2012 /* Assume that PCLK is set to 66.
V850E2/MN4 4.2.3 UARTJ Control UARTJn Control Register 0 (URTJnCTL0) The UARTJnCTL0 register controls the basic serial transfer operation of the UARTJn macros. The sample program disables the macro operations, sets the required control registers, and then, enables the UARTJn operation. Figure 4.7 URTJnCTL0 Register Format (1/2) R01AN0926EJ0100 Rev.1.
V850E2/MN4 UARTJ Control Figure 4.8 URTJnCTL0 Register Format (2/2) Setting examples URTJnPW = 1; URTJnTXE = 1; URTJnRXE = 1; URTJnBYTE = 0x00; R01AN0926EJ0100 Rev.1.
V850E2/MN4 4.2.4 UARTJ Control UARTJn Control Register 1 (URTJnCTL1) The UARTJnCTL1 register defines the data frame properties of the serial data transfers in which the UARTJn macros are used. This sample program does not use the functions related to the BF-related transmission/reception. Figure 4.9 URTJnCTL1 Register Format (1/3) R01AN0926EJ0100 Rev.1.
V850E2/MN4 UARTJ Control Figure 4.10 URTJnCTL1 Register Format (2/3) R01AN0926EJ0100 Rev.1.
V850E2/MN4 UARTJ Control Figure 4.11 URTJnCTL1 Register Format (3/3) Setting example: URTJnCTL1 = 0x5103; R01AN0926EJ0100 Rev.1.
V850E2/MN4 4.2.5 UARTJ Control FIFO Control Register 0 (URTJnFCTL0) The URTJnFCTL0 register defines the fill stages of the Rx FIFO and the Tx FIFO, at which the receive (INTUAJnTIR) and transmit (INTUAJnTIT) interrupts requests are generated. A receive interrupt request is generated when the fill stage of the receive FIFO reaches the value specified in URTJnFCTL0.URTJnSLRP[3:0]. A transmit interrupt request is generated when the fill stage of the transmit FIFO reaches the value specified in URTJnFCTL0.
V850E2/MN4 4.2.6 UARTJ Control FIFO Control Register 1 (URTJnFCTL1) The URTJnFCTL1 register controls the Rx timeout detection. A timeout error occurs, when the receive FIFO is not empty and when no receive data is stored in the receive FIFO or no data is read from the receive FIFO for a certain period of time. Figure 4.13 URTJnFCTL1 Register Format Setting example: URTJnFCTL1 = 0x3F; /* Detect timeout */ R01AN0926EJ0100 Rev.1.
V850E2/MN4 4.2.7 UARTJ Control UARTJn Status Clear Register 0 (URTJnSTC) The error flags in URTJnSTR1 are set when a data consistency error, a parity error, a framing error, and an overrun error occur. The URTJnSTC register can be used to clear the error flags in URTJnSTR1. In this sample program, the corresponding error flags are cleared by using the URTJnSTC and URTJnFSTC registers when INTUAJnTIS is detected. Figure 4.
V850E2/MN4 4.2.8 UARTJ Control FIFO Status Clear Register (URTJnFSTC) The error flags in URTJnFSTR1 are set when a timeout error, an overflow error, and an overrun error occur. The URTJnFSTC register can be used to clear the error flags in URTJnFSTR1. The transmit/receive FIFO pointers can also be cleared. In this sample program, the corresponding error flags are cleared by using the URTJnSTC and URTJnFSTC registers when INTUAJnTIS is detected. Figure 4.
V850E2/MN4 4.3 UARTJ Control Function Specifications This section describes the specifications for the functions that are used by the sample program. 4.3.1 Main Processing (main.c) [Function Name] [Function] [Arguments] [Return Value] [Startup Method] [SFRs Used] [Calling Function] [Variables] [File Name] [Notes] 4.3.2 main() Calls necessary initialization functions before entering an infinite loop. None None Enters the main function after hardware initialization.
V850E2/MN4 UARTJ Control [Function Name] [Function] [Arguments] [Return Value] [Startup Method] [SFRs Used] [Calling Function] [Variables] [File Name] [Notes] hbus_initial() Initializes the AHB bus. None None Call ETARCFG0, ETARADRS0, ETARMASK0 main() None initial.c None [Function Name] [Function] [Arguments] [Return Value] [Startup Method] [SFRs Used] [Calling Function] [Variables] [File Name] [Notes] board_initial() Sets up the initial state of the LEDs. None None Call P13 main() None initial.
V850E2/MN4 UARTJ Control [Function Name] [Function] [Arguments] [Return Value] [Startup Method] [SFRs Used] [Calling Function] [Variables] [File Name] [Notes] wait() Waits for a certain number of steps. int number None Call according to the an argument setting. None main(), int_urtj1ire(), int_urtj3ire() None initial.
V850E2/MN4 4.3.4 UARTJ Control Transmit Processing (uartj_transmit.c) [Function Name] [Function] [Arguments] [Return Value] [Startup Method] [SFRs Used] [Calling Function] [Variables] [File Name] [Notes] urtj1_transmit_initial() Initializes the UARTJ1 macro. None None Call URTJ1CTL0, URTJ1CTL1, URTJ1CTL2, URTJ1FCTL0, URTJ1FCTL1, ICURTJIC, ICURTJ1IS main() None uartj_transmit.
V850E2/MN4 4.3.5 UARTJ Control Interrupt Processing (interrupt.c) [Function Name] [Function] [Arguments] [Return Value] [Startup Method] [SFRs Used] [Calling Function] [Variables] [File Name] [Notes] int_urtj1ic () Processes the UARTJ1 macro transmit interrupt. None None Request INTUAJ1IC is present in an unmasked state. None None flag_transmit_over interrupt.
V850E2/MN4 [Function Name] [Function] [Arguments] [Return Value] [Startup Method] [SFRs Used] [Calling Function] [Variables] [File Name] [Notes] UARTJ Control int_urtj3ire () Processes the UARTJ3 macro status interrupt. None None Request INTAJ3IS is present in an unmasked state.
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