Specifications

V850E2/MN4 USB CDC (Communication Device Class) Driver
R01AN0010EJ0101 Rev.1.01 Page 28 of 117
Feb 01, 2012
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SETRQ Interrupt Processing
If the SETRQ bit in the USFA0IS0 register is 1, the SETRQC bit in the USFA0IC0 register will be cleared to 0. Next, if
both the SETCON bit in the USFA0SET register and the CONF bit in the USFA0MODS register are 1, the flag that
indicates that set configuration request was processed (usbf850_busrst_flg) is cleared.
(4)
CPUDEC Interrupt Processing
If the CPUDEC bit in the USFA0IS0 register is 1, the CPUDECC bit in the USFA0IC0 register will be cleared to 0.
Next, the USFA0E0ST register is read 8 times and the request data is acquired and decoded. If the request is a standard
request, the function usbf850_standardreq() is called and if it is a class request, the function usbf850_classreq() is called.
(5)
BKO1DT Interrupt Processing
If the BKODT bit in the USFA0IS3 register is 1, the BKODTC bit in the USFA0IC3 register will be cleared to 0. Next,
the flag that indicates that data has been received (usbf850_rdata_flg) is updated. This interrupt occurs if there is valid
data stored in the receive FIFO.