Specifications

V850E2/MN4 USB CDC (Communication Device Class) Driver
R01AN0010EJ0101 Rev.1.01 Page 25 of 117
Feb 01, 2012
(3)
Initializing the EPC Circuit
Loads the USFA0EPCCTL register with “0x00000000” to cancel the EPC reset signal.
(4)
Initializing the USB Function Buffer
Loads the USFBC register with “0x00000003” to enable the USBF buffer and floating provisions.
(5)
Setting up NAK for Control Endpoint
Sets the EP0NKA bit of the USFA0E0NA register to 1. This setting causes the hardware to respond with NAK against
all requests including automatically responded requests.
This bit is used by the software until the registration of data to be used in automatically responded requests is completed,
so that the hardware will not return unintended data in response to an automatically responded request.
(6)
Initializing the Request Data Register Area
Loads relevant registers with descriptor data that is to be used to automatically respond to GET_DESCRIPTOR
requests.
The following registers are accessed during this processing:
(a) The USFA0DSTL register is loaded with “0x01.” This setting disables the remote wakeup function and the USB
function controller operates as a self-powered device.
(b) The USFA0EnSL registers (n = 0 to 2) are loaded with “0x00.” These settings indicate that the Endpoint n are
running normally.
(c) The USFA0DSCL register is loaded with the total length (in bytes) of the data in the necessary descriptors. This
setting determines the range of the USFA0CIEn registers (n = 0 to 255) to be used.
(d) The USFA0DDn registers (n = 0 to 7) are loaded with the data for the device descriptor.
(e) The USFA0CIEn registers (n = 0 to 255) are loaded with the data for the configuration, interface, and endpoint
descriptors.
(f) The USFA0MODC register is loaded with “0x00.” This setting enables GET_DESCRIPTOR_configuration
requests to be automatically responded.
(7)
Setting up the Interfaces and Endpoints
Loads relevant registers with the number of interfaces to support, alternate setting status, and the relationship between
the interfaces and endpoints.
The following registers are accessed during this processing:
(a) The USFA0AIFN register is loaded with “0x80.” This setting enables up to two interfaces.
(b) The USFA0AAS register is loaded with “0x00.” This setting disables the alternate setting.
(c) The USFA0E1IM register is loaded with “0x40.” This setting causes Endpoint1 to be linked to Interface1.
(d) The USFA0E2IM register is loaded with “0x40.” This setting causes Endopoint2 to be linked to Interface1.
(e) The USFA0E7IM register is loaded with “0x20.” This setting causes Endopoint7 to be linked to Interface0.
(8)
Resetting NAK Setting for Control Endpoint
Sets the EP0NKA bit of the USFA0E0NA register to 0. This setting enables the resumption of responses to all requests
including automatically responded requests.