User manual

V850E2/MN4 Timer Array Unit Control
R01AN0922EJ0100 Rev.1.00 Page 8 of 54
Jan 13, 2012
Slave channel: Positive logic (TAUAnTOL.TAUAnTOLm = 0)
c c d d
a
b
a+1 a+1 b+1
b+1
Master
Slave
TAUAnTS.TAUAnTSm
TAUAnTE.TAUAnTEm
TAUAnCNTm
TAUAnCDRm
TAUAnTTOUTm
INTTAU AnIm
TAUAnTS.TAUAnTSm
TAUAnTE.TAUAnTEm
TAUAnCNTm
TAUAnCDRm
TAUAnTTOUTm
INTTAU AnIm
c
0000H
0000H
d
Figure 4.4 General Timing Diagram for PWM Output Function
For specific mode setup, see “V850E2/MN4 Hardware User Manual: Renesas MCU V850E2/Mx4 microcontrollers
(R01UH0011EJ).”