User manual

V850E2/MN4 Timer Array Unit Control
R01AN0922EJ0100 Rev.1.00 Page 7 of 54
Jan 13, 2012
4.2 Details of TAUA Setup
In this sample program, the TAUA1 is set to synchronous channel operation and PWM output function. Channel 0 in
the TAUA1 is set as a master channel and set to interval timer mode. Channel 1 in the TAUA1 is set as a slave channel
and set to synchronous channel output mode 1 in one count mode. The PWM pulse is output from the TAUA1TTOUT1
pin. The pulse cycle is set in the master channel and the duty is set in the slave channel.
The counters are enabled by setting the channel trigger bit TAUA1TS.TAUAnTS[1/0] to 1. Then, bit
TAUA1TE.TAUA1TE[1/0] is set to 1 and counting is enabled. The current value of TAUA1CDR0 is loaded into
TAUA1CNT0. The counters start counting down at that value of TAUA1CDR0. The current value of TAUA1CDR1 is
loaded into TAUA1CNT1 and the counters start to count down from these values. INTTAUA1I0 is generated in the
master channel and the PWM signal is output by setting and resetting the TAUA1TTOUT1 (slave).
When the counter of the master channel reaches 0000H and a pulse cycle time has elapsed, INTTAUA1I0 is generated.
The value of TAUA1CDR0 is loaded into TAUA1CNT0 and then the counter starts to count down from this value.
The INTTAUA1I0 of the master channel triggers the counter of the slave channel. The current value of TAUA1CDR1
(slave) is loaded into TAUA1CNT1 (slave) and then the counter starts to count down from this value. The
TAUA1TTOUT1 signal becomes active. When the counter reaches 0000H (duty time has elapsed), INTTAUA1I1 is
generated and the TAUA1TTOUT1 signal becomes inactive. The counter returns to FFFFH and awaits the next
INTTAUA1I0 from the master channel (the start of the next pulse cycle).
The counters can be stopped by setting TAUA1TT.TAUA1TT[1/0] to 1 in the master and slave channel. Then,
TAUA1TE.TAUA1TE[1:0] are set to 0. TAUA1CNT1, TAUA1CNT0, and TAUA1TTOUT1 of master and slave
channel stop but retain their values. The counters can be restarted by setting channel trigger bits
TAUA1TS.TAUA1TS[1/0] to 1.
Pulse period = (TAUA1CDR0 (master)  1) × count clock cycle
Duty cycle [%] = (TAUA1CDR1 (slave) / (TAUA1CDR0 (master)  1)) × 100%
In this sample program, the duty cycle is set to 80%.
The general timing diagram for the PWM output function is shown below.
TAUAnTS.TAUAnTSm
CK3 to Ck0
CK3 to CK0
TAUAnTTINm
TAUAnTS.TAUAnTSm
TAUAnTTINm
Master
Sl ave
TAUAnTRO
TAUAnTROm
TAUAnTRO
TAUAnTROm
TAU AnT RO
TAU AnT ROm
Count
clock
Simultaneou s rewr ite
trigger from uppe r
channel
Star t trigger fr om maste r
Co unt
clock
Slave:
One count mode
Master :
Interval timer mode
Tr igger from upper channel
Star t trigger fr om ma ster
INTfrom master
INT from upper channel
INT
INT
TAUAnTO .
TAUAnTOm
TAUAnCNTm
TAUAnCDRm
TAUAnCDRm
Edge
selector
Cloc k s elect or
Sta rt &
capture
tr ig ger
Start &
capture
trigger
Edge
selector
Trigger fr om lower chan nel
INT fro m master
INT from upper channel
Clock selectorTrigger selectorT r igg er se le c to r
TAUAnCNTm
Figure 4.3 Block Diagram for PWM Output Function