User manual

V850E2/MN4 Timer Array Unit Control
R01AN0922EJ0100 Rev.1.00 Page 51 of 54
Jan 13, 2012
4.4.10 TAUJn Channel Output Level Registers
• TAUJn channel output register (TAUJnTO)
This register specifies and reads the level of TAUJnTTOUTm. In this sample program, the TAUJ does not use the
output function.
• TAUJn channel output level register (TAUJnTOL)
This register specifies the output logic of the channel output bit (TAUJnTO.TAUJnTOm). In this sample program, the
TAUJ does not use the output function.
4.4.11 TAUJn Simultaneous Rewrite Registers
• TAUJn channel reload data enable register (TAUJnRDE)
This register enables/disables simultaneous rewrite of data registers TAUJnCDRm and TAUJnTOLm. In this sample
program, the TAUJ does not use the simultaneous rewrite function.
• TAUJn channel reload data mode register (TAUJnRDM)
This register determines when the simultaneous rewrite control signal is generated. In this sample program, the TAUJ
does not use the simultaneous rewrite function.
• TAUJn channel reload data trigger register (TAUJnRDT)
This register triggers the simultaneous rewrite pending state. In this sample program, the TAUJ does not use the
simultaneous rewrite function.
• TAUJn channel reload status register (TAUJnRSF)
This flag register indicates the simultaneous rewrite status. In this sample program, the TAUJ does not use the
simultaneous rewrite function.