User manual

V850E2/MN4 Timer Array Unit Control
R01AN0922EJ0100 Rev.1.00 Page 34 of 54
Jan 13, 2012
• TAUAn channel reload data mode register (TAUAnRDM)
This register determines when the simultaneous rewrite control signal is generated. In this sample program, the
simultaneous rewrite control signal is set as the signal that is generated when the counter in the master channel starts
counting.
Figure 4.29 TAUAnRDM Register Format
Setting example
TAUA1RDM = 0x0000; /* cocurrent at beginning of master count */
• TAUAn channel reload data control register (TAUAnRDC)
This register specifies the channel in which the INTTAUAnIm signal that triggers simultaneous rewrite is generated.
This sample program does not use the TAUAnRDC register because TAUAnRDS.TAUAnRDSm is set to 0.
• TAUAn channel reload data trigger register (TAUAnRDT)
This register triggers the simultaneous rewrite pending state. This sample program does not use this function.
• TAUAn channel reload status register (TAUAnRSF)
This flag register indicates the simultaneous rewrite status. This sample program does not use this function.