User manual

V850E2/MN4 Timer Array Unit Control
R01AN0922EJ0100 Rev.1.00 Page 22 of 54
Jan 13, 2012
Setting examples
TAUA1CMOR0 = 0x0801;
/* CK0, master, software trigger count, interval mode, int at start */
TAUA1CMOR1 = 0x0409;
/* CK0, slave, INT of master as trigger, one count mode, start trigger effective */
• TAUAn channel mode user register (TAUAnCMURm)
This register specifies the type of valid edge detection used for the TAUAnTTINm input. In this sample program, the
TAUA does not use edge detection function.
• TAUAn channel status register (TAUAnCSRm)
This register indicates the count direction and the overflow status of channel m counter. In this sample program, the
TAUA does not use edge detection function.
• TAUAn channel status clear register (TAUAnCSCm)
This registers is a trigger register for clearing the overflow flag TAUAnCSRm.TAUAnOVF of channel m. In this
sample program, the TAUA does not use edge detection function.
• TAUAn channel start trigger register (TAUAnTS)
This register enables the counter for each channel.