User manual

V850E2/MN4 Timer Array Unit Control
R01AN0922EJ0100 Rev.1.00 Page 18 of 54
Jan 13, 2012
• TAUAn channel mode OS register (TAUAnCMORm)
This register controls channel m operation.
In this sample program, channel 0 in the TAUA1 is set as a master channel and set to interval timer mode. When the
counter is triggered by software trigger, INTTAUA1I0 is generated at the start of operation. Channel 1 is set as a slave
channel, is set to one count mode, and enables the start trigger during operation by using INTTAUA1I0 of the master
channel as a start trigger.
Figure 4.14 TAUAnCMORm Register Format (1/4)