APPLICATION NOTE V850E2/MN4 Timer Array Unit Control R01AN0922EJ0100 Rev.1.00 Jan 13, 2012 Introduction This application note explains how to set up the 16-bit timer array unit A (TAUA) and 32-bit timer array unit J (TAUJ) and also gives an outline of the operation and describes the procedure for using a sample program. The sample program makes the TAUA generate the PWM signal and output the signal to the TAUJ and makes the TAUJ measure the width of the signal input from the TAUA.
V850E2/MN4 1. Timer Array Unit Control Overview This application note illustrates the usage examples of the 16-bit TAUA (timer array unit A) and 32-bit TAUJ (timer array unit J). In the TAUA, channel 0 is set as a master channel, channel 1 is set as a slave channel, and the PWM signal is output from the TAUA1TTOUT1 pin in synchronous channel operation.
V850E2/MN4 2. Timer Array Unit Control Usage Environment This section explains the circuit diagram and development environment to run this sample program. 2.1 Circuit Diagram See “V850E2/MN4 Target Board User Manual: QB-V850E2MN4DUAL-TB (R20UT0683XJ)” for the details of the circuit diagram. The P3_1 pin functions as the TAUA1TTOUT1 pin to output the PWM signal and the P2_1 pin functions as the TAUJ0TTIN0 pin to input the PWM signal. The P3_1 pin must be connected to the P2_1 pin. 2.
V850E2/MN4 3. Timer Array Unit Control Software This section describes the file organization of the sample program. 3.1 File Organization The sample program consists of the files that are listed below. File Name (Tool Structure) crtE.s V850E2MN4.dir taua.h main.c initial.c taua_control.c tauj_control.c interrupt.
V850E2/MN4 4. Timer Array Unit Control Sample Application This section explains how to set up the TAUA and the TAUJ. 4.1 Flow Charts The flow charts of this sample program are shown below. 4.1.1 Main Processing The main processing sets up the ports and the timer array units. The timers are started, the TAUA is made to generate the PWM pulse, and then, the TAUJ is made to measure the pulse width. Figure 4.1 Main Processing R01AN0922EJ0100 Rev.1.
V850E2/MN4 4.1.2 Timer Array Unit Control Interrupt Processing Flow The INTTUAJ0I0 interrupt function processing checks for an overflow to calculate the input PWM signal width (HIGH). Figure 4.2 Interrupt Processing Flow R01AN0922EJ0100 Rev.1.
V850E2/MN4 4.2 Timer Array Unit Control Details of TAUA Setup In this sample program, the TAUA1 is set to synchronous channel operation and PWM output function. Channel 0 in the TAUA1 is set as a master channel and set to interval timer mode. Channel 1 in the TAUA1 is set as a slave channel and set to synchronous channel output mode 1 in one count mode. The PWM pulse is output from the TAUA1TTOUT1 pin. The pulse cycle is set in the master channel and the duty is set in the slave channel.
V850E2/MN4 Timer Array Unit Control Slave channel: Positive logic (TAUAnTOL.TAUAnTOLm = 0) TAUAnTS.TAUAnTSm TAUAnTE.TAUAnTEm TAUAnC NTm 0000H TAUAnC DRm b a TAUAnTTOUTm IN TTAUAnIm Master Slave TAUAnTS.TAUAnTSm TAUAnTE.TAUAnTEm TAUAnC NTm 0000H T AUAnCDRm d c TAUAnTTOUTm IN TTAUAnIm a+1 c a+1 c b+1 d b+1 d Figure 4.4 General Timing Diagram for PWM Output Function For specific mode setup, see “V850E2/MN4 Hardware User Manual: Renesas MCU V850E2/Mx4 microcontrollers (R01UH0011EJ).
V850E2/MN4 4.3 Timer Array Unit Control Details of TAUJ Setup In this sample program, the TAUJ0 is set to independent channel operation and signal width measurement function. Channel 0 is set to capture & one count mode. The TAUJ0TTIN0 pin is used to measure the input signal width (HIGH). The counter is enabled by setting the channel trigger bit TAUJ0TS.TAUJ0TS0 to 1. Then, bit TAUJ0TE.TAUJ0TE0 is set to 1 and counting is enabled.
V850E2/MN4 4.4 Timer Array Unit Control Register Setup This section explains how to set up the relevant registers according to the flow charts shown in section 4.1. The registers described below must be configured to control the timer I/O. 4.4.1 Port Setup In this sample program, the pin P3_1, which is used to generate the PWM signal in the TAUA, is used as TAUA1TTOUT1. The pin P2_1, which is used to measure the input signal width in the TAUJ, is used as TAUJ0TTIN0.
V850E2/MN4 4.4.2 Timer Array Unit Control TAUAn Prescaler Registers • TAUAn prescaler clock select register (TAUAnTPS) This register specifies the CK0, CK1, CK2, and CK3_PRE prescaler clocks for all channels. CK3 is generated by dividing CK3_PRE by the factor specified in TAUAnBRS. In this sample program, CK0 is specified. Figure 4.7 TAUAnTPS Register Format (1/4) R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control Figure 4.8 TAUAnTPS Register Format (2/4) R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control Figure 4.9 TAUAnTPS Register Format (3/4) R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control Figure 4.10 TAUAnTPS Register Format (4/4) Setting example TAUA1TPS = 0x000a; /* CK0:PCLK / 2^10 */ • TAUAn prescaler baudrate value register (TAUAnBRS) This register specifies the division factor of prescaler clock CK3. CK3 is generated by dividing CK3_PRE by the factor specified in this register plus one. The PCLK prescaler for CK3_PRE is specified in TAUAnTPS.TAUAnPRS3[3:0]. This register does not use CK3. Setting this register is unnecessary. R01AN0922EJ0100 Rev.
V850E2/MN4 4.4.3 Timer Array Unit Control TAUAn Control Registers • TAUAn channel data register (TAUAnCDRm) This register functions either as a compare register or a capture register, depending on the operation mode specified in TAUAnCMORm.TAUAnMD[4:1]. In this sample program, the cycle of the PWM pulse is set in TAUA1CDR0 and the duty of the pulse is set in TAUA1CDR1. Figure 4.11 TAUAnCDRm Register Format Setting example TAUA1CDR0 = 4999; TAUA1CDR1 = 4000; R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control • TAUAn channel counter register (TAUAnCNTm) This register is the channel m counter register. Figure 4.12 TAUAnCNTm Register Format (1/2) R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control Figure 4.13 TAUAnCNTm Register Format (2/2) R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control • TAUAn channel mode OS register (TAUAnCMORm) This register controls channel m operation. In this sample program, channel 0 in the TAUA1 is set as a master channel and set to interval timer mode. When the counter is triggered by software trigger, INTTAUA1I0 is generated at the start of operation. Channel 1 is set as a slave channel, is set to one count mode, and enables the start trigger during operation by using INTTAUA1I0 of the master channel as a start trigger.
V850E2/MN4 Timer Array Unit Control Figure 4.15 TAUAnCMORm Register Format (2/4) R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control Figure 4.16 TAUAnCMORm Register Format (3/4) R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control Figure 4.17 TAUAnCMORm Register Format (4/4) R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control Setting examples TAUA1CMOR0 = 0x0801; /* CK0, master, software trigger count, interval mode, int at start */ TAUA1CMOR1 = 0x0409; /* CK0, slave, INT of master as trigger, one count mode, start trigger effective */ • TAUAn channel mode user register (TAUAnCMURm) This register specifies the type of valid edge detection used for the TAUAnTTINm input. In this sample program, the TAUA does not use edge detection function.
V850E2/MN4 Timer Array Unit Control Figure 4.18 TAUAnTS Register Format Setting example TAUA1TS = 0x0003; R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control • TAUAn channel enable status register (TAUAnTE) This register indicates whether the counter is enabled/disabled. Figure 4.19 TAUAnTE Register Format R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control • TAUAn channel stop trigger register (TAUAnTT) This register stops the counter for each channel. Figure 4.20 TAUAnTT Register Format R01AN0922EJ0100 Rev.1.
V850E2/MN4 4.4.4 Timer Array Unit Control TAUAn Output Registers • TAUAn channel output enable register (TAUAnTOE) This register enables/disables independent channel output mode controlled by software. In this sample program, the TAUA1 is set to PWM output function. Channel 1 in the TAUA1 enables the independent macro output function. Figure 4.21 TAUAnTOE Register Format Setting example TAUA1TOE = 0x0002; R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control • TAUAn channel output mode register (TAUAnTOM) This register specifies the output mode of each channel. In this sample program, the TAUA1 is set to PWM output function. Channel 1 in the TAUA1 is set to synchronous channel operation mode. Figure 4.22 TAUAnTOM Register Format Setting example TAUA1TOM = 0x0002; R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control • TAUAn channel output configuration register (TAUAnTOC) This register specifies the output mode of each channel in combination with TAUAnTOMm. In this sample program, the TAUA1 is set to PWM output function. Channel 1 in the TAUA1 is set to synchronous channel operation mode 1. Figure 4.23 TAUAnTOC Register Format Setting example TAUA1TOC = 0x0000; R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control • TAUAn channel dead time output enable register (TAUAnTDE) This register enables/disables the dead time operation for each channel. In this sample program, the TAUA disables dead time operation. Figure 4.24 TAUAnTDE Register Format Setting example TAUA1TDE = 0x0000; /* dead time prohibit */ • TAUAn channel dead time output mode register (TAUAnTDM) This register specifies when dead time is added during dead time output.
V850E2/MN4 Timer Array Unit Control • TAUAn channel real-time output enable register (TAUAnTRE) This register enables/disables real-time output. This program disables real-time output. Figure 4.25 TAUAnTRE Register Format Setting example TAUA1TRE = 0x0000; /* real time output prohibit */ • TAUAn channel real-time output control register (TAUAnTRC) This register controls the real-time output trigger for each channel. This sample program does not use the real-time output function.
V850E2/MN4 4.4.5 Timer Array Unit Control TAUAn Channel Output Level Registers • TAUAn channel output register (TAUAnTO) This register specifies and reads the level of TAUAnTTOUTm. In this sample program, the functions of specifying and reading the level of TAUAnTTOUTm are not used. • TAUAn channel output level register (TAUAnTOL) This register specifies the output logic of the channel output bit (TAUAnTO.TAUAnTOm). In this sample program, the level of TAUAnTTOUTm is set to positive logic. Figure 4.
V850E2/MN4 4.4.6 Timer Array Unit Control TAUAn Simultaneous Rewrite Registers • TAUAn channel reload data enable register (TAUAnRDE) This register enables/disables simultaneous rewrite of data registers TAUAnCDRm and TAUAnTOLm. In this sample program, the TAUA generates the PWM signal in synchronous channel operation. Simultaneous rewrite is enabled in channels 0 and 1 in the TAUA1. Figure 4.27 TAUAnRDE Register Format Setting example TAUA1RDE = 0x0003; R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control • TAUAn channel reload data control channel select register (TAUAnRDS) This register selects the channel that controls simultaneous rewrite. In this sample program, the master channel is set as a channel that monitors the simultaneous rewrite trigger in the TAUA1. Figure 4.28 TAUAnRDS Register Format0 Setting example TAUA1RDS = 0x0000; R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control • TAUAn channel reload data mode register (TAUAnRDM) This register determines when the simultaneous rewrite control signal is generated. In this sample program, the simultaneous rewrite control signal is set as the signal that is generated when the counter in the master channel starts counting. Figure 4.
V850E2/MN4 4.4.7 Timer Array Unit Control TAUJn Prescaler Registers • TAUJn prescaler clock select register (TAUJnTPS) This register specifies the CK0, CK1, CK2, and CK3_PRE prescaler clocks for all channels. CK3 is generated by the factor specified in TAUJnBRS. In this sample program, CK0 is specified. Figure 4.30 TAUJnTPS Register Format (1/3) R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control Figure 4.31 TAUJnTPS Register Format (2/3) R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control Figure 4.32 TAUJnTPS Register Format (3/3) Setting example TAUJ0TPS = 0x0000; /* CK0:PCLK / 2^0 */ • TAUJn prescaler baudrate value register (TAUJnBRS) This register specifies the division factor of prescaler clock CK3. CK3 is generated by dividing CK3_PRE by the factor specified in this register plus one. The PCLK prescaler for CK3_PRE is specified in TAUJnTPS.TAUJnPRS3[3:0]. This register does not use CK3. Setting this register is unnecessary. R01AN0922EJ0100 Rev.
V850E2/MN4 4.4.8 Timer Array Unit Control TAUJn Control Registers • TAUJn channel data register (TAUJnCDRm) This register functions either as a compare register or as a capture register, depending on the operation mode specified in TAUJnCMORm.TAUJnMD[4:1]. In this sample program, the TAUJ0TTIN0 signal width is estimated by a combination of the values of TAUJ0CDR0 and TAUJ0CSR0.TAUJnOVF. Figure 4.
V850E2/MN4 Timer Array Unit Control • TAUJn channel counter register (TAUJnCNTm) This register is the channel m counter register. Figure 4.34 TAUJnCNTm Register Format R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control Figure 4.35 TAUJnCNTm read values R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control • TAUJn channel mode OS register (TAUJnCMORm) This register controls channel m operation. In this sample program, channel 0 in the TAUJ0 is set to capture & one count mode and disables the start trigger during operation by using the valid edge of the TAUJ0TTIN0 input signal as an external start trigger and the reverse edge as a stop trigger. Figure 4.36 TAUJnCMORm Register Format (1/3) R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control Figure 4.37 TAUJnCMORm Register Format (2/3) R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control Figure 4.38 TAUJnCMORm Register Format (3/3) Setting example TAUJ0CMOR0 = 0x020c; /* CK0, TTIN trigger edge count, capture and one count mode, no int at start */ R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control • TAUJn channel mode user register (TAUJnCMURm) This register specifies the type of valid edge detection used for the TAUJnTTINm input. In this sample program, the TAUJ is set to single operation signal width measurement and measures the width of the pulse input from TAUJ0TTIN0. When both edges are detected, the high level width is measured by regarding the start trigger as the rising edge and the stop trigger as the falling edge. Figure 4.
V850E2/MN4 Timer Array Unit Control • TAUJn channel status register (TAUJnCSRm) This register indicates the count direction and the overflow status of channel m counter. Figure 4.40 TAUJnCSRm Register Format R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control • TAUJn channel status clear register (TAUJnCSCm) This registers is a trigger register for clearing the overflow flag TAUJnCSRm.TAUJnOVF of channel m. Figure 4.41 TAUJnCSCm Register Format R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control • TAUJn channel start trigger register (TAUJnTS) This register enables the counter for each channel. Figure 4.42 TAUJnTS Register Format Setting example TAUJ0TS = 0x0001; R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control • TAUJn channel enable status register (TAUJnTE) This register indicates whether the counter is enabled/disabled. Figure 4.43 TAUJnTE Register Format R01AN0922EJ0100 Rev.1.
V850E2/MN4 Timer Array Unit Control • TAUJn channel stop trigger register (TAUJnTT) This register stops the counter for each channel. Figure 4.44 TAUJnTT Register Format R01AN0922EJ0100 Rev.1.
V850E2/MN4 4.4.9 Timer Array Unit Control TAUJn Output Registers • TAUJn channel output enable register (TAUJnTOE) This register enables or disables independent channel output mode controlled by software. In this sample program, the TAUJ is set to signal width measurement function. The TAUJ disables the independent macro output function. Figure 4.
V850E2/MN4 4.4.10 Timer Array Unit Control TAUJn Channel Output Level Registers • TAUJn channel output register (TAUJnTO) This register specifies and reads the level of TAUJnTTOUTm. In this sample program, the TAUJ does not use the output function. • TAUJn channel output level register (TAUJnTOL) This register specifies the output logic of the channel output bit (TAUJnTO.TAUJnTOm). In this sample program, the TAUJ does not use the output function. 4.4.
V850E2/MN4 4.5 Timer Array Unit Control Function Specifications This section describes the specifications for the functions that are used by the sample program. 4.5.1 Main (main.c) [Function Name] [Function] [Arguments] [Return Value] [Startup Method] [SFRs Used] [Calling Function] [Variables] [File Name] [Notes] 4.5.2 Initialization Processing (initial.c) [Function Name] [Function] [Arguments] [Return Value] [Startup Method] [SFRs Used] [Calling Function] [Variables] [File Name] [Notes] 4.5.
V850E2/MN4 4.5.4 Timer Array Unit J Control (tauj_control.c) [Function Name] [Function] [Arguments] [Return Value] [Startup Method] [SFRs Used] [Calling Function] [Variables] [File Name] [Notes] 4.5.5 Timer Array Unit Control tauj0_initial() Sets up the independent signal width measurement mode. None None Call TAUJ0TPS, TAUJ0BRS, TAUJ0CMOR0, TAUJ0CMUR0, TAUJ0TOE, TAUJ0TOM, TAUJ0TOC, TAUJ0TOL, TAUJ0RDE, TAUJ0RDM, TAUJ0RDT, ICTAUJ0I0, TAUJ0TS main() None tauj_control.
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