Specifications

V850E2/MN4 CSIH Control
R01AN0924EJ0100 Rev.1.00 Page 6 of 40
Feb 10, 2012
The basic communication specifications are shown below.
Memory mode Direct access mode Dual buffer mode
Receive I/F CSIH3
Transmit I/F CSIH0
Transfer direction MSB first
Parity bits during
transmission/reception
No parity bit
Data length 8 bits
Baud rate 64 kbps
FIFO size None
64 bytes (each of transmit FIFO
and receive FIFO
Communication data length 6 bytes 9 bytes
JOB (jobs) 2 jobs None
EDL (extended data length) None
LBM (loop-back mode) None
SS (slave select) None
1.1 Initialization
The general registers and functional pins are initialized.
<Port setup>
• Port n function control expansion registers (PFCEn)
• Port n function control registers (PFCn)
• Port n mode control registers (PMCn)
• Port n mode registers (PMn)
1.2 CSIH Setup
The registers listed below are set up to control the operation of the CSIH. See section 4.2 for the details.
<CSIH control setup>
• CSIHn control register 0 (CSIHnCTL0)
• CSIHn control register 1 (CSIHnCTL1)
• CSIHn control register 2 (CSIHnCTL2)
• CSIHn memory control register 0 (CSIHnMCTL0)
• CSIHn memory control register 1 (CSIHnMCTL1)
• CSIHn memory control register 2 (CSIHnMCTL2)
• CSIHn configuration register x (CSIHnCFGx)
1.3 Interrupt Enabling
Interrupts are enabled by the EI instruction.