Specifications

V850E2/MN4 CSIH Control
R01AN0924EJ0100 Rev.1.00 Page 32 of 40
Feb 10, 2012
4.3 Memory Modes
The CSIH supports FIFO mode, dual buffer mode, transmit-only buffer mode, and direct access mode as memory
modes. The memory mode can be changed by resetting CSIHnMCTL0.CSIHnMMS[1:0]. The conditions for starting
CSIH data transfer and the interrupt timing depends on the memory mode, the operation mode, and the transfer mode.
Table 4.1 Start of Data Transfer
Transfer Mode
Memory Mode and
Operating Mode
Transmit-Only and
Transmit/Receive
Receive
Master Writes to the CSIHnTX0 register Writes to the CSIHnTX0 register FIFO mode
Direct access mode
Slave
Writes to the CSIHnTX0 register
and starts the master clock
Receives a clock from the master
Master Sets CSIHnMCTL2.BTST to 1 Sets CSIHnMCTL2.BTST to 1
Transmit-only
buffer mode
Slave
Sets CSIHnMCTL2.BTST to 1
and starts the master clock
Receives a clock from the master
Master Sets CSIHnMCTL2.BTST to 1 Sets CSIHnMCTL2.BTST to 1
Dual buffer mode
Slave
Sets CSIHnMCTL2.BTST to 1
and starts the master clock
Receives a clock from the master