Specifications

V850E2/MN4 CSIH Control
R01AN0924EJ0100 Rev.1.00 Page 24 of 40
Feb 10, 2012
4.2.5 CSIH Configuration Register x (CSIHnCFGx)
The CSIHnCFGx registers specify the prescaler, the parity, the data length, the recessive configuration for broadcasting,
the serial data direction, the clock phase and the data phase, the idle enforcement configuration, the idle timing, the hold
timing, the inter-data timing, and the setup timing for each chip select signal CSIHCSSx.
In master mode, one or more chip select signals can be used. If several slaves are connected to the master, the chip
select signals can be used to address one or more of the slaves. Only a selected slave is then enabled for communication.
A value must be set in the bit for each chip select signal according to the baud rate. In this sample program, these bits
are set to initial values.
Figure 4.13 CSIHnCFGx Register Format (1/5)