Specifications

V850E2/MN4 CSIH Control
R01AN0924EJ0100 Rev.1.00 Page 23 of 40
Feb 10, 2012
Figure 4.12 CSIHnCTL1 Register Format (3/3)
CSIHnCTL1 = 0x00010040; /* TIC at start;CS0 inactive;JOB mode enable */
/* Output initial CSIHTSCO value at high level */
/* Transmit status interrupt request is generated at beginning of
transmission */
/* Set chip select signal CS0 to active low*/
/* Disable extended data length mode */
/* Enable job mode */
/* Disable data consistency check */
/* Chip select signals retain active level */
/* Set loopback mode inactive */
/* No interrupt delay mode */
/* Disable handshake function */
/* Disable slave selection (SS) */
CSIHnCTL1 = 0x00000000; /* Normal interrupt timing */
/* CS0 inactive */
/* Disable job mode */
CSIHnCTL1 = 0x00000000; /* Set chip select signals to active low */
/* hand shaking disable */