Specifications

V850E2/MN4 CSIH Control
R01AN0924EJ0100 Rev.1.00 Page 14 of 40
Feb 10, 2012
4.1.5 Slave Dual-Buffer Receive-Only Mode
Slave dual-buffer receive-only mode is started by setting the CSIHnMCTL2.CSIHnBTST bit to 1 and then detecting
external clock CSIHTSCK.
te
Figure 4.5 Flowchart of Slave Dual-Buffer Receive-Only Mode
Initialize CSIHn
Start
Set BIST bit to 1
Start of reception
YES
YES
YES
NO
NO
NO
Set user receive end flag
END
Has communication
clock CSIHnTSCK been
detected?
Has CSIHnTIR
interrupt occurred?
Read data from CSIHnRX0W register
by receive data read processing
Have all data
been read?
Remark 1. The broken lines indicate hardware processing