APPLICATION NOTE V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Feb 10, 2012 Introduction This application note explains how to set up the CSIH (clocked three-wire serial interface) and also gives an outline of the operation and describes the procedures for using a sample program. The sample program transmits and receives data between the CSIH0 and CSIH3. The CSIH0 transmits data in master mode, while the CSIH3 receives data in slave mode.
V850E2/MN4 1. CSIH Control Overview This application note explains the following four operation modes of the CSIH as usage examples: • Master dual-buffer transmit-only mode • Slave dual-buffer receive-only mode • Master direct-access transmit-only mode • Slave direct-access receive-only mode In master mode, the serial communication clock is generated by the internal baudrate generator (BRG) and supplied by signal CSIHnTSCK. In slave mode, another device is the communication master.
V850E2/MN4 CSIH Control The main points in slave dual-buffer receive-only mode are illustrated below. : Flow of processing Main loop processing : Interrupt Receive status interrupt processing Start of transmission Interrupt Receive status interrupt No End of transmission ? Yes End of processing The receive data is stored in the user receive array and then set the user receive end flag is set to 1.
V850E2/MN4 CSIH Control The main points in master direct-access transmit-only mode (Job mode is enabled) are illustrated below. : Flow of processing Transmit data generation processing JOB1 JOB2 : Interrupt First, an user-supplied array is defined and the transmit data is divided into two jobs. Main loop processing Transmit status interrupt processing Start of transmission Transmission is started when data is stored in CSIH0TX0W.
V850E2/MN4 CSIH Control The main points in slave direct-access receive-only mode are illustrated below. : Flow of processing : Interrupt Main loop processing Receive status interrupt processing Interrupt Start of reception Receive status interrupt No End of reception ? The receive data is stored in the user receive array. When all data have been transmitted, the user flag is set to 1. ......
V850E2/MN4 CSIH Control The basic communication specifications are shown below. Memory mode Receive I/F Transmit I/F Transfer direction Parity bits during transmission/reception Data length Baud rate FIFO size Direct access mode Communication data length JOB (jobs) EDL (extended data length) LBM (loop-back mode) SS (slave select) 1.
V850E2/MN4 1.4 CSIH Control Main Loop Processing • The operation of data transfer via the CSIH depends on the memory mode. In dual buffer mode, the transmitting CSIH0 transmits nine bytes of data and the receiving CSIH3 receives the nine bytes of data from the CSIH0. The internal RAM has nine bytes (one byte (one block data) × nine) of an area for each of the user transmit array to store transmit data and the user receive array to store receive data.
V850E2/MN4 2. CSIH Control Usage Environment This section provides the circuit diagram and operating environment of the hardware on which this sample program is to run. 2.1 Circuit Diagram See “V850E2/MN4 Target Board User Manual: QB-V850E2MN4DUAL-TB (R20UT0683XJ)” for the details of the circuit diagram. This sample program performs CSI communication between the CSIH0 and the CSIH3. The CSIH0 transmits data in master mode and the CSIH3 receives the data in slave mode.
V850E2/MN4 3. CSIH Control Software This section describes the organization of the compressed files to be downloaded. 3.1 File Organization The compressed files to be downloaded is summarized below. File Name (Tool Structure) crtE.s startup.s V850E2MN4.dir V850E2_MN4 CSIH.ld vector.s csih.h main.c initial.c csih_transmit.c csih_receive.c interrupt.
V850E2/MN4 4. CSIH Control Sample Application This section explains how to set up the CSIH functions. 4.1 Flow Charts The flow charts of this sample program are given below. The pertinent subroutines are entered according to the operating mode that is set up by the user. 4.1.1 Main Processing The main processing disables maskable interrupts first. After each setup ends, the maskable interrupts and transmit/receive status interrupts are enabled.
V850E2/MN4 4.1.2 CSIH Control Master Direct-Access Transmit-Only Mode Master direct-access transmit-only mode is started by writing transmit data to the CSIHnTX0W register. Forty-eight bits (six bytes) of transmit data are divided into two jobs before transmission. The communication data length is eight bits.
V850E2/MN4 4.1.3 CSIH Control Slave Direct-Access Receive-Only Mode Slave direct-access receive-only mode is started by detecting external clock CSIHTSCK. Start Initialize CSIHn Has communication clock CSIHnTSCK been detected? NO YES Start of reception Has CSIHnTIR interrupt occurred? NO YES Read data from CSIHnRX0W register by receive data read processing NO End of reception? YES Set user receive end flag End Remark 1. The broken lines indicate hardware processing. Figure 4.
V850E2/MN4 4.1.4 CSIH Control Master Dual-Buffer Transmit-Only Mode Master dual-buffer transmit-only mode is started by setting the CSIHnMCTL2.CSIHnBTST bit to 1. Start Initialize CSIHn Write transmit data to CSIHnTX0W register Have all data been written? NO YES Set BTST bit to 1 Start transmission Have CSIHnTIC interrupt occurred? NO YES Set user transmit end flag End Remark 1. The broken lines indicate hardware processing Figure 4.
V850E2/MN4 4.1.5 CSIH Control Slave Dual-Buffer Receive-Only Mode Slave dual-buffer receive-only mode is started by setting the CSIHnMCTL2.CSIHnBTST bit to 1 and then detecting external clock CSIHTSCK. Start Initialize CSIHn Set BIST bit to 1 Has communication clock CSIHnTSCK been detected? NO YES Start of reception Has CSIHnTIR interrupt occurred? NO YES Read data from CSIHnRX0W register by receive data read processing Have all data been read? NO YES Set user receive end flag END Remark 1.
V850E2/MN4 4.1.6 CSIH Control Communication Error Interrupt Processing If a communication error occurs, a communication error interrupt is generated. Then, the communication error interrupt processing is executed. The communication is stopped and the SFR error flag is cleared. The CSIHn is reset at the same time. Status interrupt INT_CSIHTIRE Clear error flag Reset CSIHn End of processing Figure 4.6 Communication Error Interrupt Processing R01AN0924EJ0100 Rev.1.
V850E2/MN4 4.2 CSIH Control Register Setup This section explains how to set up the relevant registers according to the flow charts shown in section 4.1. The registers described below must be configured to control the CSIH. 4.2.1 Port Setup The program described in this application note executes serial transmission/reception by using two macros, the CSIH0 and the CSIH3. The relevant ports must be set up so that the pins for the CSIH0 and the CSIH3 are enabled. The LEDs are connected to port 13.
V850E2/MN4 4.2.2 CSIH Control CSIH Control Register 2 (CSIHnCTL2) The CSIHnCTL2 register selects the communication clock. In master mode, the transmission baud rate can be selected by the CSIHnPRS[2:0] bits and the CSIHnBRS[11:0] bits in the CSIHnCTL2 register. The maximum available baud rate is Pclk/4 in master mode and Pclk/6 in slave mode. The minimum available baud rate is Pclk/524160 in both modes.
V850E2/MN4 CSIH Control Setting example CSIHnCTL2 = 0x2104; CSIHnCTL2 = 0xE000; R01AN0924EJ0100 Rev.1.
V850E2/MN4 4.2.3 CSIH Control CSIH Control Register 0 (CSIHnCTL0) The CSIHnCTL0 register controls the operation clock, enables or disables transmission and reception, and specifies the use for the CSIH memory. It forces the stop of communication at the end of the current job. Figure 4.8 CSIHnCTL0 Register Format (1/2) R01AN0924EJ0100 Rev.1.
V850E2/MN4 CSIH Control Figure 4.9 CSIHnCTL0 Register Format (2/2) CSIHnCTL0 = 0x00; CSIHnPWR = 1; CSIHnTXE = 1; CSIHnRXE = 1; CSIHnMBS = 0; CSIHnMBS = 1; CSIHnJOBE = 1; R01AN0924EJ0100 Rev.1.
V850E2/MN4 4.2.4 CSIH Control CSIH Control Register 1 (CSIHnCTL1) The CSIHnCTL1 register controls the communication. It mainly specifies the interrupt timing and interrupt delay mode and selects the active output level of each chip select signal and the chip select signal operation to perform after the last data is transferred. Figure 4.10 CSIHnCTL1 Register Format (1/3) R01AN0924EJ0100 Rev.1.
V850E2/MN4 CSIH Control Figure 4.11 CSIHnCTL1 Register Format (2/3) R01AN0924EJ0100 Rev.1.
V850E2/MN4 CSIH Control Figure 4.12 CSIHnCTL1 Register Format (3/3) CSIHnCTL1 = 0x00010040; CSIHnCTL1 = 0x00000000; CSIHnCTL1 = 0x00000000; R01AN0924EJ0100 Rev.1.
V850E2/MN4 4.2.5 CSIH Control CSIH Configuration Register x (CSIHnCFGx) The CSIHnCFGx registers specify the prescaler, the parity, the data length, the recessive configuration for broadcasting, the serial data direction, the clock phase and the data phase, the idle enforcement configuration, the idle timing, the hold timing, the inter-data timing, and the setup timing for each chip select signal CSIHCSSx. In master mode, one or more chip select signals can be used.
V850E2/MN4 CSIH Control Figure 4.14 CSIHnCFGx Register Format (2/5) R01AN0924EJ0100 Rev.1.
V850E2/MN4 CSIH Control Figure 4.15 CSIHnCFGx Register Format (3/5) R01AN0924EJ0100 Rev.1.
V850E2/MN4 CSIH Control Figure 4.16 CSIHnCFGx Register Format (4/5) R01AN0924EJ0100 Rev.1.
V850E2/MN4 CSIH Control Figure 4.17 CSIHnCFGx Register Format (5/5) CSIHnCFG0 = 0x08000000; R01AN0924EJ0100 Rev.1.
V850E2/MN4 4.2.6 CSIH Control CSIH Memory Control Register 0 (CSIHnMCTL0) The CSIHnMCTL0 register selects the memory mode and timeout setting. FIFO mode, dual buffer mode, transmit-only buffer mode, and direct access mode can be set in the CSIH as memory modes. The sample program uses only dual buffer mode. It does not detect timeout time. Figure 4.18 CSIHnMCTL0 Register Format CSIH0MCTL0 = 0x0100; R01AN0924EJ0100 Rev.1.
V850E2/MN4 4.2.7 CSIH Control CSIH Status Clear Register 0 (CSIHnSTCR0) The CSIH can detect five errors: data consistency error, parity error, overrun error, timeout error, and overflow error. The parity error, data consistency error, and timeout error can be individually enabled or disabled by the CSIHnSTCR0 register. When any of these errors is detected, receive error interrupt CSIHTIRE is generated.
V850E2/MN4 /* Clear status flags to 0 */ CSIHnTMOEC = 1; CSIHnOFEC = 1; CSIHnPEC = 1; CSIHnOVEC = 1; CSIHnPCT = 1; CSIHnDCEC = 1; R01AN0924EJ0100 Rev.1.
V850E2/MN4 4.3 CSIH Control Memory Modes The CSIH supports FIFO mode, dual buffer mode, transmit-only buffer mode, and direct access mode as memory modes. The memory mode can be changed by resetting CSIHnMCTL0.CSIHnMMS[1:0]. The conditions for starting CSIH data transfer and the interrupt timing depends on the memory mode, the operation mode, and the transfer mode. Table 4.
V850E2/MN4 4.4 CSIH Control Function Specifications This section describes the specifications for the functions that are used by the sample program. 4.4.1 Main Processing (main.c) [Function Name] [Function] [Arguments] [Return Value] [Startup Method] [SFRs Used] [Calling Function] [Variables] [File Name] [Notes] 4.4.2 main () Calls necessary initialization functions before entering an infinite loop. None None Enters the main function after hardware initialization.
V850E2/MN4 CSIH Control [Function Name] [Function] [Arguments] [Return Value] [Startup Method] [SFRs Used] [Calling Function] [Variables] [File Name] [Notes] hbus_initial() Initializes the AHB bus. None None Call ETARCFG0, ETARADRS0, ETARMASK0 main() None initial.c None [Function Name] [Function] [Arguments] [Return Value] [Startup Method] [SFRs Used] [Calling Function] [Variables] [File Name] [Notes] board_initial() Sets up the initial state of the LEDs. None None Call P13 main() None initial.
V850E2/MN4 CSIH Control [Function Name] [Function] [Arguments] [Return Value] [Startup Method] [SFRs Used] [Calling Function] [Variables] [File Name] [Notes] display() Controls the LEDs according to the state of the relevant flags. None None Call P13 main() flag_transmit_over, flag_receive_over, flag_error initial.
V850E2/MN4 CSIH Control [Function Name] [Function] [Arguments] [Return Value] [Startup Method] [SFRs Used] [Calling Function] [Variables] [File Name] [Notes] csih_receive_2_initial() The CSIH3 macro performs initialization in dual-buffer receive-only mode. None None Call CSIH3CTL0, CSIH3CTL1, CSIH3CTL2, CSIH3CFG0, ICCSIH3IR csih_receive_initial() None csih_receive.
V850E2/MN4 [Function Name] [Function] [Arguments] [Return Value] [Startup Method] [SFRs Used] CSIH Control [Calling Function] [Variables] [File Name] [Notes] csih_transmit_2_initial() The CSIH0 macro performs initialization in dual-buffer transmit-only mode. None None Call CSIH0CTL0, CSIH0CTL1, CSIH0CTL2, CSIH0CFG0, ICCSIH0IC, CSIH0MCTL0, CSIH0MCTL2 csih_transmit_initial() None csih_transmit.
V850E2/MN4 4.4.5 CSIH Control Interrupt Processing (interrupt.c) [Function Name] [Function] [Arguments] [Return Value] [Startup Method] [SFRs Used] [Calling Function] [Variables] [File Name] [Notes] int_csih0ic() Processes CSIH0 macro transmit status interrupt. None None Request CSIH0TIC is present in an unmasked state. CSIH0CTL0 None flag_mode, flag_job_transmit, flag_transmit_over interrupt.
V850E2/MN4 [Function Name] [Function] [Arguments] [Return Value] [Startup Method] [SFRs Used] [Calling Function] [Variables] [File Name] [Notes] CSIH Control int_csih3ire() Processes CSIH3 macro communication error interrupt. None None Request CSIH3TIRE is present in an unmasked state. CSIH3STCR0, CSIH3CTL0 None flag_error, point_receive, point_transmit, count interrupt.c None R01AN0924EJ0100 Rev.1.
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